DFPIC165X Datasheet, PDF (5/6 Pages) Digital Core Design – High Performance 8-bit RISC Microcontroller

PERFORMANCE
The following table gives a survey about
the Core area and performance in the
ALTERA® devices after Place & Route:
Device
Speed
grade
Logic Cells
F_max
CYCLONE
-6
551
105 MHz
CYCLONE II -6
547
108 MHz
STRATIX
-5
551
108 MHz
STRATIX II
-3
456
178 MHz
STRATIX GX -5
551
109 MHz
APEX II
-7
635
73 MHz
APEX20KC
-7
635
68 MHz
APEX20KE
-1
635
56 MHz
APEX20K
-1
635
45 MHz
ACEX1K
-1
648
50 MHz
FLEX10KE
-1
648
48 MHz
*CPU – consisted of ALU, Control Unit, Bus Controller, Hardware Stack,
256 B RAM, 4k of Program memory
Core performance in ALTERA® devices
IMPROVEMENT
Most instruction of DFPIC165X is executed
within 2 CLK cycles. Except the conditional
program memory branches in case that the
condition of branch instruction is met. The
table below shows sample instructions execu-
tion times:
Mnemonic DFPIC165X PIC16C54
operands (CLK cycles) (CLK cycles)
ADDWF
2
4
ANDWF
2
4
RLF
2
4
BCF
DECFSZ
INCFSZ
BTFSC
BTFSS
2
2(4)¹
2(4)¹
2(4)¹
2(4)¹
4
4(8)¹
4(8)¹
4(8)¹
4(8)¹
CALL
2
8
GOTO
2
8
RETLW
2
8
1_{- number of clock in case that result of operation is 0.}
Impr.
2
2
2
2
2
2
2
2
4
4
4
DFPIC&DRPIC FAMILY OVERVIEW
The family of DCD DFPICXX & DRPICXX IP Cores combine a high–performance, low cost, and
small compact size, offering the best price/performance ratio in the IP Market. The DCD’s Cores are
dedicated for use in cost-sensitive consumer products, computer peripherals, office automation,
automotive control systems, security and telecommunication applications.
DCD’s DFPICXX & DRPICXX IP Cores family contains four 8-bit microcontroller Cores to best
meet your needs: DFPIC165X 12-bit program word, DFPIC1655X 14-bit program word, and
DRPIC1655X and DRPIC166X single cycle microcontrollers with 14-bit program word. All three mi-
crocontroller cores are binary compatible with widely accepted PIC16C5X and PIC16CXXX. They
employ a modified RISC architecture two or four times faster than the original ones.
The DFPICXXX & DRPICXX IP Cores are written in pure VHDL/VERILOG HDL languages which
make them technologically independent. All of the DFPICXX & DRPICXX family members supports a
power saving SLEEP mode and allows the user to configure the watchdog time-out period and a
number of hardware stack levels. DFPICXX & DRPICXX can be fully customized according to cus-
tomer needs.
Design
DFPIC165X 2k 128 12 33 24
--
--
- - 2 - 2 - 2 700
DFPIC1655X 64k 512 14 35 16
--
--
518
2 * 3 900
DRPIC1655X 64k 512 14 35 32
--
--
518
4 * 4 800
DRPIC166X 64k 512 14 35 32
558
4 * 6 700
* Optional
DFPIC & DRPIC family of High Performance Microcontroller Cores
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