DFPIC165X Datasheet, PDF (4/6 Pages) Digital Core Design – High Performance 8-bit RISC Microcontroller

Indirect addressing is possible by using the
INDF register. Any instruction using INDF reg-
ister actually accesses data pointed to by the
file select register FSR. Reading INDF register
indirectly will produce 00h. Writing to the INDF
register indirectly results in a no-operation. An
effective 8-bit address is obtained from an 8-
bit FSR register.
Timer 0 – Main system’s timer and prescaler.
The DFPIC165X Timer operates in two
modes: 8-bit timer or 8-bit counter. In the
“timer mode”, timer registers are incremented
every 4 CLK periods. When the prescaler is
assigned into the TIMER prescale ration can
be divided by 2, 4 .. 256. In the “counter
mode” the timer register is incremented every
falling or rising edge of T0CKI pin, dependent
on T0SE bit in OPTION register.
Watchdog Timer – it is a free running timer.
WDT has own clock input separate from sys-
tem clock. It means that the WDT will run
even if the system clock is stopped by execu-
tion of SLEEP instruction. During normal op-
eration, a WDT timeout generates a Watch-
dog reset. If the device is in SLEEP mode the
WDT timeout causes the device to wake-up
and continue with normal operation.
I/O Ports – Block contains DFPIC165X’s gen-
eral purpose I/O ports and data direction reg-
isters (TRIS). The DFPIC165X has three 8-bit
full bi-directional ports PORT A, PORT B and
PORT C. Read and write accesses to the I/O
port are performed via their corresponding
SFR’s PORTA, PORTB, PORTC. The reading
instruction always reads the status of Port
pins. Writing instructions always write into the
Port latches. Each port’s pin has an corre-
sponding bit in TRISA, TRISB and TRISC reg-
isters. When the bit of TRIS register is set this
means that the corresponding bit of port is
configured as an input (output drivers are set
into the High Impedance).
OPTIONAL
PERIPHERALS
There are also available an optional pe-
ripherals, not included in presented
DFPIC165X Microcontroller Core. The op-
tional peripherals, can be implemented in mi-
crocontroller core upon customer request.
● Full duplex UART
● SPI – Master and Slave Serial Peripheral
Interface
○ Supports speeds up ¼ of system clock
○ Mode fault error
○ Write collision error
○ Software selectable polarity and phase of se-
rial clock SCK
○ System errors detection
○ Allows operation from a wide range of system
clock frequencies (build-in 5-bit timer)
○ Interrupt generation
● PWM – Pulse Width Modulation Timer
○ 2 independent 8-bit PWM channels, concate-
nated on one 16-bit PWM channel
○ Software-selectable duty from 0% to 100% and
pulse period
○ Software-selectable polarity of output wave-
form
● I2C bus controller - Master
○ 7-bit and 10-bit addressing modes
○ NORMAL, FAST, HIGH speeds
○ Multi-master systems supported
○ Clock arbitration and synchronization
○ User defined timings on I2C lines
○ Wide range of system clock frequencies
○ Interrupt generation
● I2C bus controller - Slave
○ NORMAL speed 100 kbs
○ FAST speed 400 kbs
○ HIGH speed 3400 kbs
○ Wide range of system clock frequencies
○ User defined data setup time on I2C lines
○ Interrupt generation
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