DFPIC165X Datasheet, PDF (1/6 Pages) Digital Core Design – High Performance 8-bit RISC Microcontroller

DFPIC165X
High Performance
8-bit RISC Microcontroller
ver 2.01
OVERVIEW
The DFPIC165X is a low-cost, high per-
formance, 8-bit, fully static soft IP Core, dedi-
cated for operation with fast memory (typi-
cally on-chip). The core has been designed
with a special concern about low power con-
sumption.
The DFPIC165X is software compatible
with the industry standard PIC16C54,
PIC16C55, PIC16C56, PIC16C57 and
PIC16C58. It employs a modified RISC
architecture (2 times faster than original
implementation).
The DFPIC165X have enhanced core
features and configurable hardware stack.
The separate instruction and data buses allow
a 12 bit wide instruction word with the
separate 8 -bit wide data. The DFPIC165X
typically achieve a 2:1 code compression and
a 8:1 speed improvement over other 8-bit
microcontrollers in its class. The Core has 24
I/O lines and an 8-bit timer/counter with an 8-
bit programmable prescaller.
The power-down mode SLEEP allow user
to reduce power consumption. User can wake
up the controller from SLEEP through an user
reset or watchdog overflow. An integrated
Watchdog Timer with it's own clock signal
provides protection against software lock-up.
The DFPIC165X Microcontroller fits
perfectly in applications ranging from high-
speed automotive and appliance motor control
to low-power remote transmitters/receivers,
pointing devices and telecom processors.
Built-in power save mode and small used area
in programmable devices make this IP perfect
for applications applications with space and
power consumption limitations.
DFPIC165X is delivered with fully auto-
mated testbench and complete set of tests
allowing easy package validation at each
stage of SoC design flow.
CPU FEATURES
● Software compatible with industry standard
PIC16C5X
● Harvard architecture 2 times faster com-
pared to original implementation
● 33 instructions
● 12 bit wide instruction word
● Up to 256 bytes of internal Data Memory
● Up to 4K bytes of Program Memory
● Configurable hardware stack
● Power saving SLEEP mode
● Fully synthesizable, static synchronous
design with no internal tri-states
● Scan test ready
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