DFPIC165X Datasheet, PDF (2/6 Pages) Digital Core Design – High Performance 8-bit RISC Microcontroller

PERIPHERALS
● Three 8 bit I/O ports
○ Three 8-bit corresponding TRIS registers
● Timer 0
○ 8-bit timer/counter
○ Readable and Writable
○ 8-bit software programmable prescaler
○ Internal or external clock select
○ Edge select for external clock
● Watchdog Timer
○ Configurable Time out period
○ 7-bit software programmable prescaler
○ Dedicated independent Watchdog Clock input
DELIVERABLES
♦ Source code:
◊ VHDL Source Code or/and
◊ VERILOG Source Code or/and
◊ Encrypted Megafunction or/and
◊ plain text EDIF
♦ VHDL & VERILOG test bench environ-
ment
◊ Active-HDL automatic simulation macros
◊ ModelSim automatic simulation macros
◊ Tests with reference responses
♦ Technical documentation
◊ Installation notes
◊ HDL core specification
◊ Datasheet
♦ Synthesis scripts
♦ Example application
♦ Technical support
◊ IP Core implementation support
◊ 3 months maintenance
● Delivery the IP Core updates, minor
and major versions changes
● Delivery the documentation updates
● Phone & email support
LICENSING
Comprehensible and clearly defined licensing
methods without royalty fees make using of IP
Core easy and simply.
Single Design license allows use IP Core in
single FPGA bitstream and ASIC implementa-
tion.
Unlimited Designs, One Year licenses allow
use IP Core in unlimited number of FPGA bit-
streams and ASIC implementations.
All trademarks mentioned in this document
are trademarks of their respective owners.
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time restric-
tion except One Year license where time of
use is limited to 12 months.
● Single Design license for
○ VHDL, Verilog source code called HDL Sour-
ce
○ Encrypted, or plain text EDIF called Netlist
● One Year license for
○ Encrypted Netlist only
● Unlimited Designs license for
○ HDL Source
○ Netlist
● Upgrade from
○ HDL Source to Netlist
○ Single Design to Unlimited Designs
CONFIGURATION
The following parameters of the DFPIC165X
core can be easy adjusted to requirements of
dedicated application and technology. Con-
figuration of the core can be prepared by ef-
fortless changing appropriate constants in
package file. There is no need to change any
parts of the code.
• RAM memory type
• RAM size
• Program Memory size
•
Number
levels
of
hardware
stack
• SLEEP mode
• WATCHDOG Timer
• Timer system
• PORTS A,B,C
- synchronous
- asynchronous
- up to 256
- default 128
- up 4 kWords
- default 2k
- 1-8
- default 2
- used
- unused
- used / width
- unused
- used
- unused
- used
- unused
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