D16450 Datasheet, PDF (5/6 Pages) Digital Core Design – Configurable UART

PERFORMANCE
The following table gives a survey about
the Core area and performance in the
ALTERA® devices after Place & Route:
Device
Speed
grade
Logic Cells
F_max
CYCLONE
-6
301
190 MHz
CYCLONE 2 -6
303
222 MHz
STRATIX
-5
301
213 MHz
STRATIX 2
-3
248
283 MHz
STRATIXGX -5
301
212 MHz
MERCURY
-5
350
222 MHz
EXCALIBUR -1
340
137 MHz
APEX II
-7
340
145 MHz
APEX20KC -7
340
143 MHz
APEX20KE
-1
340
122 MHz
APEX20K
-1
340
83 MHz
ACEX1K
-1
363
99 MHz
FLEX10KE
-1
363
98 MHz
Core performance in ALTERA® devices
D16X50 UARTS FAMILY OVERVIEW
The family of DCD D16X50 UART IP Cores combine a high–performance, low cost, and small
compact size, offering the best price/performance ratio in the IP Market. The DCD’s Cores are
dedicated for use in cost-sensitive consumer products, computer peripherals, office automation,
automotive control systems, security and telecommunication applications.
The D16X50 IP Cores are written in pure VHDL/VERILOG HDL languages which make them
technologically independent. All of the D16X50 IP Cores can be fully customized according to
customer needs.
Design
D16450
1
D16550
1
D16750
1
D16552
2
D16752
2
D16754
4
*-Optional
-
-
2* 16
2* 64
4* 16
4* 64
8* 64
-
-
-
-
-
-
-
D16X50 family of Configurable UARTs with FIFO IP Cores
-* -*
-* -*
-* -*
-* -*
-* -*
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