D16450 Datasheet, PDF (3/6 Pages) Digital Core Design – Configurable UART

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CONFIGURATION
The following parameters of the D16450 core
can be easy adjusted to requirements of
dedicated application and technology.
Configuration of the core can be prepared by
effortless changing appropriate constants in
package file. There is no need to change any
parts of the code.
• Baud generator
- enable
- disable
• External RCLK source
- enable
- disable
• External BAUDCLK source
- enable
- disable
• Modem Control logic
- enable
- disable
• SCR Register
- enable
- disable
DESIGN FEATURES
The functionality of the D16450 core was
based on the Texas Instruments TL16C450.
The following characteristics differentiate the
D16450 from Texas Instruments devices:
● The bi-directional data bus has been split
into two separate buses: datai(7:0),
datao(7:0)
● Signals rd2 and wr2, xin, and xout have
been removed from interface
● Signal ADS and address latch have been
removed
● The DLL, DLM and THR registers are
reset to all zeros
● TEMT and THRE bits of Line Status
Register, are reset during the second
clock rising edge following a THR write
● RCLK clock is replaced by global clock
CLK, internally divided by BAUD factor.
● Asynchronous microcontroller interface is
replaced by equivalent Universal interface
● All latches implemented in original 16450
devices are replaced by equivalent flip-flop
registers, with the same functionality
SYMBOL
rst
clk
rclk
baudclk
baudout
intr
datai(7:0)
address(2:0)
datao(7:0)
wr
rd
D16450
ddis
cs
si
so
cts
rts
dsr
dtr
dcd
out1
ri
out2
baudclken
rclken
PINS DESCRIPTION
PIN
TYPE
DESCRIPTION
rst
input Global reset
clk
input Global clock
datai[7:0]
input Parallel data input
addr[2:0]
input Address bus
cs
input Chip select input
wr
input Write input
rd
input Read input
rclk
input Receiver clock
baudclk
input Baud generator clock
si
input Serial data input
cts
input Clear to send input
dsr
input Data set ready input
dcd
input Data carrier detect input
ri
input Ring indicator input
baudclken
input Baud generator clock enable
rclken
input Receiver clock enable
baudout
output Baud generator output
datao[7:0]
output Parallel data output
so
output Serial data output
ddis
output Driver disable output
rts
output Request to send output
dtr
output Data terminal ready output
out1
output Output 1
out2
output Output 2
intr
output Interrupt request output
Note: When enabled RCLK and BAUDCLK pins
frequency should be at least two times lower
than CLK, 2*f_RCLK< f_CLK
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