D16450 Datasheet, PDF (4/6 Pages) Digital Core Design – Configurable UART

APPLICATION
addr
CPU ale
addr
latch
datao(7:0)
datai(7:0)
we
rd
cs
int
addr(2:0)
D16450
clk
rst
baudclk
rclk
datai(7:0)
so
datao(7:0)
si
wr
rts
rd
dtr
cs
dsr
intr
dcd
cts
out1
ri
out2
baudclken
rclken
EIA
Drivers
Typical D16450 and processor connection is
shown in figure above.
BLOCK DIAGRAM
Data Bus Buffer - The data Bus Buffer
accepts inputs from the system bus and
generates control signals for the other D14750
functional blocks. Address bus ADDR(2:0)
selects one of the register to be read
from/written into. Both RD and WE signals are
active low, and are qualified by CS; RD and
WE are ignored unless the D16450 has been
selected by holding CS low.
Baud Generator - The D16450 contains a
programmable 16 bit baud generator that
divides clock input by a divisor in the range
between 1 and (2¹⁶–1). The output frequency
of the baud generator is 16× the baud rate.
The formula for the divisor is:
divisor = ^frequency
baudrate *16
Two 8-bit registers, called divisor latches DLL
and DLM, store the divisor in a 16-bit binary
format. These divisor latches must be loaded
during initialization of the D16450 in order to
ensure desired operation of the baud
generator. When either of the divisor latches
is loaded, a 16-bit baud counter is also loaded
on the CLK rising edge following the write to
DLL or DLM to prevent long counts on initial
load.
Modem Control Logic controls the interface
with the MODEM or data set (or a peripheral
device emulating a MODEM).
Interrupt Controller - D16450 consists fully
prioritized interrupt system controller. It
controls interrupt requests to the CPU and
interrupt priority. Interrupt controller contains
Interrupt Enable (IER) and Interrupt
Identification (IIR) registers.
addr(2:0)
datai(7:0)
datao(7:0)
rd
wr
cs
ddis
baudclk
baudclken
baudout
clk
rst
Data Bus
Buffer
Interrupt
Controller
Baud
Generator
Receiver
Control
&
Shift Register
rclk
rclken
si
Transmitter
Control
&
so
Shift Register
Modem
control
logic
rts
cts
dtr
dsr
dcd
ri
out1
out2
Receiver Control - Receiving starts when the
falling edge on Serial Input (SI) during IDLE
State is detected. After starting the SI input is
sampled every 16 internal baud cycles as it is
shown in figure below. When the logic 1 state
is detected during START bit it means that the
False Start bit was detected and receiver back
to the IDLE state.
Transmitter Control module controls
transmission of written to THR (Transmitter
Holding register) character via serial output
SO. The new transmission starts on the next
overflow signal of internal baud generator,
after writing to THR register or Transmitter
FIFO. Transmission control contains THR
register and transmitter shift register.
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.