D16450 Datasheet, PDF (2/6 Pages) Digital Core Design – Configurable UART

● Fully programmable serial-interface
characteristics:
○ 5-, 6-, 7-, or 8-bit characters
○ Even, odd, or no-parity bit generation and
detection
○ 1-, 1½-, or 2-stop bit generation
○ Baud generation
● Complete status reporting capabilities
● Line break generation and detection.
Internal diagnostic capabilities:
○ Loop-back controls for communications link
fault isolation
○ Break, parity, overrun, framing error
simulation
● Technology independent HDL Source
Code
● Full prioritized interrupt system controls
● Fully synthesizable static design with no
internal tri-state buffers
DELIVERABLES
♦ Source code:
◊ VHDL Source Code or/and
◊ VERILOG Source Code or/and
◊ Encrypted, or plain text EDIF netlist
♦ VHDL & VERILOG test bench
environment
◊ Active-HDL automatic simulation macros
◊ ModelSim automatic simulation macros
◊ Tests with reference responses
♦ Technical documentation
◊ Installation notes
◊ HDL core specification
◊ Datasheet
♦ Synthesis scripts
♦ Example application
♦ Technical support
◊ IP Core implementation support
◊ 3 months maintenance
● Delivery the IP Core updates, minor
and major versions changes
● Delivery the documentation updates
● Phone & email support
APPLICATIONS
● Serial Data communications applications
● Modem interface
All trademarks mentioned in this document
are trademarks of their respective owners.
LICENSING
Comprehensible and clearly defined licensing
methods without royalty fees make using of IP
Core easy and simply.
Single Design license allows use IP Core in
single FPGA bitstream and ASIC
implementation.
Unlimited Designs, One Year licenses allow
use IP Core in unlimited number of FPGA
bitstreams and ASIC implementations.
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time
restriction except One Year license where
time of use is limited to 12 months.
● Single Design license for
○ VHDL, Verilog source code called HDL
Source
○ Encrypted, or plain text EDIF called Netlist
● One Year license for
○ Encrypted Netlist only
● Unlimited Designs license for
○ HDL Source
○ Netlist
● Upgrade from
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.