SLK2511B Datasheet, PDF (14/21 Pages) DB Lectro Inc – OC-48/24/12/3 SONET/SDH MULTIRATE TRANSCEIVER

SLK2511B
SLLS763B – JANUARY 2007 – REVISED MARCH 2007
www.ti.com
TIMING REQUIREMENTS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
REFERENCE CLOCK (REFCLK)
Frequency tolerance⁽¹⁾
–20
20 ppm
Duty cycle
40% 50% 60%
Jitter
12 kHz to 20 MHz
3 ps rms
PLL PERFORMANCE SPECIFICATIONS
PLL startup lock time
Acquisition lock time
V_DD, V_DDC = 2.3 V, after REFCLK is stable
Valid SONET signal or PRBS OC-48
2031
1 ms
Bit Times
SERIAL TRANSMITTER/RECEIVER CHARACTERISTICS
V_(ODD) = |STXDOP-STXDON|, transmit
differential output voltage under
de-emphasis
PRE1 = 0, PRE2 = 0, Rt = 50,
See Table 5 and Figure 1
PRE1 = 1, PRE2 = 0
PRE1 = 0, PRE2 = 1
650 850 1000
550 750 900 _mV
540 700 860
PRE1 = 1, PRE2 = 1
500 650 800
V_(CMT)
V_(CMR)
I_l
R_l
C_I
t_{d(TX_Latency)}
t_{d(RX_Latency)}
Transmit common mode voltage range
Receiver Input voltage requirement,
V_ID=|SRXDIP–SRXDIN|
Receiver common mode voltage range
Receiver input leakage
Receiver differential impedance
Receiver input capacitance
Rt = 50Ω
1100 1250 1400 mV
150
mV
1100
-550
80
1250
100
2250 mV
550 µ A
120 Ω
1 pF
50
Bit Times
50
(1) The ±20 ppm tolerance is required to meet SONET/SDH requirements. For non-SONET/SDH compliant systems, looser tolerances may
apply.
SERIAL DIFFERENTIAL SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
t_t Differential signal rise time (20% to 80%) R_L = 50Ω
t_j Output jitter
Jitter-free data, 12 kHz to 20 MHz, RLOOP = 1
Jitter tolerance
RLOOP = 1, See Figure 2
Jitter transfer
RLOOP = 1, See Figure 2
MIN TYP MAX UNIT
80 100 140 ps
0.05
0.1 UI_(pp)
14
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