SLK2511B Datasheet, PDF (1/21 Pages) DB Lectro Inc – OC-48/24/12/3 SONET/SDH MULTIRATE TRANSCEIVER

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SLK2511B
SLLS763B – JANUARY 2007 – REVISED MARCH 2007
OC-48/24/12/3 SONET/SDH MULTIRATE TRANSCEIVER
FEATURES
• Fully Integrated SONET/SDH Transceiver to
Support Clock/Data Recovery and
Multiplexer/Demultiplexer Functions
• Supports OC-48, OC-24, OC-12, Gigabit
Ethernet, and OC-3 Data Rate With Autorate
Detection
• Supports Transmit Only, Receiver Only,
Transceiver and Repeater Functions in a
Single Chip Through Configuration Pins
• Supports SONET/SDH Frame Detection
• On-Chip PRBS Generation and Verification
• Supports 4-Bit LVDS (OIF99.102) Electrical
Interface
• Parity Checking and Generation for the LVDS
Interface
• Single 2.5-V Power Supply
• Interfaces to Back Plane, Copper Cables, or
Optical Modules
• Hot Plug Protection
• Low Jitter PECL Compatible Differential Serial
Interface With Programmable De-Emphasis for
the Serial Output
• On-Chip Termination for LVDS and PECL
Compatible Interface
• Receiver Differential Input Thresholds 150 mV
Min
• Supports SONET Loop Timing
• Low Power CMOS
• ESD Protection >2 kV
• 155-MHz or 622-MHz Reference Clock
• Maintains Clock Output in Absence of Data
• Local and Remote Loopback
• 100-Pin PZP Package With PowerPAD™
Design With 5-mm × 5-mm (Typ) Heatsink
DESCRIPTION
The SLK2511B is a single chip multirate transceiver IC used to derive high-speed timing signals for
SONET/SDH based equipment. The chip performs clock and data recovery, serial-to-parallel/parallel-to-serial
conversion and frame detection function conforming to the SONET/SDH standards.
The device can be configured to operate under OC-48, OC-24, OC-12, or OC-3 data rates through the rate
selection pins or the autorate detection function. An external reference clock operating at 155.52 MHz or 622.08
MHz is required for the recovery loop, and it also provides a stable clock source in the absence of serial data
transitions.
The SLK2511B accepts 4-bit LVDS parallel data/clock and generates a NRZ SONET/SDH-compliant signal at
OC-3, OC-12, OC-24, or OC-48 rates. It also recovers the data and clock from the serial SONET stream and
demultiplexes it into 4-bit LVDS parallel data for full duplex operation. TXDATA0 and RXDATA0 are the first bits
that are transmitted and received in time, respectively. The serial interface is a low jitter, PECL compatible
differential interface.
The SLK2511B provides a comprehensive suite of built-in tests for self-test purposes including local and remote
loopback and PRBS (2⁷-1) generation and verification.
The device comes in a 100-pin VQFP package that requires a single 2.5-V supply with 3.3-V tolerant inputs on
the control pins. The SLK2511B is power efficient, dissipating less than 900 mW at 2.488 Gbps, the OC-48 data
rate, and it is characterised for operation from –40°C to 85°C.
AVAILABLE PACKAGE OPTIONS⁽¹⁾
T_A
–40°C to 85°C
PowerPAD QUAD (PZP)
SLK2511BPZP
(1) For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI website at www.ti.com
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated