SLK2511B Datasheet, PDF (13/21 Pages) DB Lectro Inc – OC-48/24/12/3 SONET/SDH MULTIRATE TRANSCEIVER

SLK2511B
www.ti.com
SLLS763B – JANUARY 2007 – REVISED MARCH 2007
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TTL
V_IH
High-level input voltage
V_IL
Low-level input voltage
I_IH
Input high current
I_IL
Input low current
V_OH
High-level output voltage
V_OL
Low-level output voltage
C_I
Input capacitance
LVDS INPUT SIGNALS
V_I
Input voltage
V_ID(th)
Input differential threshold voltage
See Figure 5
t_r/t_f
Input transition time
C_I
Input capacitance
R_I
Input differential impedance
t_su
Input setup time requirement
t_h
Input hold time requirement
T_(duty)
Input clock duty cycle
LVDS OUTPUT SIGNALS
V_OD
V_OS
V_OD
V_OS
I_(SP), I_(SN),
I_(SPN)
I_off
t_{(cq_min)}
t_{(cq_max)}
t_r/t_f
Output differential voltage
Output common mode voltage
Change VOD between 1 and 0
Change VOS between 1 and 0
Output short circuit current
Power-off current
Clock-output time
Output transition time
Output clock duty cycle
Data output to FRAME_SYNC delay
TEST CONDITIONS
V_DD = MAX, V_IN = 2 V
V_DD = MAX, V_IN =0.4 V
I_OH = –1 mA
I_OH = 1 mA
Assumes 60% / 40% duty cycle
Assumes 55% / 45% duty cycle
20% to 80%
On-chip termination
See Figure 8
See Figure 8
R_L = 100 ±1%
Outputs shorted to ground or shorted together
V_DD = 0 V
See Figure 7
20% to 80%
MIN TYP MAX UNIT
2
3.6
V
0.80
V
40 µA
–40
µA
2.10 2.3
V
0.25 0.5
V
4 pF
825
1575 mV
250
mV
200
375 ps
3 pF
80 100 120
Ω
300
ps
300
ps
40%
60%
300
1070
100
45%
4
800
1375
mV
25
25
24 mA
10 µA
100
ps
100
300 ps
55%
7 Bit times
(OC-48 = 622.08 MHz, Clock Rates With t_r/t_f ≤ 500 ps)
250
200
150
100
50
0
40 42 44 46 48 50 52 54 56 58 60
Input Duty-Cycle - %
Figure 5. LVDS Differential Input Voltage vs Input Duty Cycle
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