SLK2511B Datasheet, PDF (12/21 Pages) DB Lectro Inc – OC-48/24/12/3 SONET/SDH MULTIRATE TRANSCEIVER

SLK2511B
SLLS763B – JANUARY 2007 – REVISED MARCH 2007
ABSOLUTE MAXIMUM RATINGS⁽¹⁾
over operating free-air temperature range (unless otherwise noted)
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V_DD
Supply voltage
TTL input terminals
Voltage range
LVDS terminals
Any other terminal except aboven
P_D
Package power dissipation
T_stg
Storage temperature
Electrostatic discharge
T_A
Characterized free-air operating temperature range
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
VALUE
UNIT
–0.3 to 3
V
–0.3 to 4
V
–0.3 to 3
V
–0.3 to V_DD + 0.3
V
See Dissipation Rating Table
–65 to 150
°C
HBM: 2 kv
–40 to 85
°C
260
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS
PACKAGE
PZP ⁽²⁾
PZP ⁽³⁾
T_A≤ 25°C
POWER RATING
3.4 W
2.27 W
DERATING FACTOR⁽¹⁾
ABOVE T_A = 25°C
33.78 mW/°C
22.78 mW/°C
(1) This is the inverse of the traditional junction-to-ambient thermal resistance (R_θJA).
(2) 2 oz trace and copper pad with solder.
(3) 2 oz trace and copper pad without solder.
T_A = 85°C
POWER RATING
1.3 W
0.911 W
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
V_DD
Supply voltage
P_D
Power dissipation
Shutdown current
Frequency = 2.488 Gb/sec, PRBS pattern
Enable = 0, VDDA, VDD pins, VDD = max
T_A
Operating free-air temperature
MIN
2.375
– 40
NOM
2.5
900
20
MAX
2.625
1100
85
UNIT
V
mW
µA
°C
START-UP SEQUENCE
To ensure proper start up, follow one of the following steps when powering up the SLK2511B.
1. Keep ENABLE (pin 44) low until power supplies and reference clock have become stable.
2. Drive ENABLE (pin 44) low for at least 30 ns after power supplies and reference clock have become
stable.
The following step is recommended with either of the above two sequences.
3. Drive RESET low for at least 10 ns after link has become stable to center the TXFIFO.
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