3D6701 Datasheet, PDF (3/4 Pages) Data Delay Devices, Inc. – MONOLITHIC CLOCK SYNCHRONIZER (SERIES 3D6701)

DEVICE SPECIFICATIONS (Cont’d)
3D6701
TABLE 2: DC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 3.0V to 5.25V)
PARAMETER
SYMBOL MIN
Static Supply Current*
I_DD
High Level Input Voltage
V_IH
2.0
Low Level Input Voltage
V_IL
High Level Input Current
I_IH
Low Level Input Current
I_IL
High Level Output Current
I_OH
Low Level Output Current
I_OL
4.0
TYP
20.0
-35.0
15.0
MAX
0.8
1.0
1.0
-4.0
UNITS
mA
V
V
A
A
mA
mA
NOTES
V_IH = V_DD
V_IL = 0V
V_DD=4.75V, V_OH=2.4V
V_DD=4.75V, V_OL=0.4V
*IDD will vary slightly for different input clock frequencies
TABLE 3: AC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 3.0V to 3.6V)
PARAMETER
SYMBOL MIN
Input Frequency
F_IN
30
Duty Cycle
DC(F_IN)
40
Gate Frequency
G_IN
Gate Inactive (Low)
G_IN,LOW
200
Gate-to-Out Delay
D_INH
Gate-to-Out Delay
Jitter
F_OUT Period Jitter
Reset Time
ΔD_INH
T_RES
TYP
MAX UNITS
80
MHz
60
%
1
MHz
ns
157
ns
136
ns
120
ns
420
ps
460
ps
780
ps
50
ps
10
ns
NOTES
F_IN=50MHz
F_IN=62MHz
F_IN=80MHz
F_IN=50MHz
F_IN=62MHz
F_IN=80MHz
TABLE 4: AC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 4.75V to 5.25V)
PARAMETER
SYMBOL MIN
Input Frequency
F_IN
50
Duty Cycle
DC(F_IN)
40
Gate Frequency
G_IN
Gate Inactive (Low)
G_IN,LOW
125
Gate-to-Out Delay
D_INH
Gate-to-Out Delay
Jitter
F_OUT Period Jitter
Reset Time
ΔD_INH
T_RES
TYP
MAX UNITS
100
MHz
60
%
2
MHz
ns
138
ns
118
ns
106
ns
640
ps
700
ps
520
ps
50
ps
10
ns
NOTES
F_IN=50MHz
F_IN=62MHz
F_IN=80MHz
F_IN=50MHz
F_IN=62MHz
F_IN=80MHz
Doc #14015
DATA DELAY DEVICES, INC.
3
6/9/2014
3 Mt. Prospect Ave. Clifton, NJ 07013