3D6701 Datasheet, PDF (2/4 Pages) Data Delay Devices, Inc. – MONOLITHIC CLOCK SYNCHRONIZER (SERIES 3D6701)

3D6701
THEORY OF OPERATION
The 3D6701 clock synchronizer architecture is
shown in Figure 2. The F_IN input is assumed to
come from a stable clock source, such as a
crystal oscillator. A rising edge on the G_IN input
initiates the phase detection process. Once the
phase of the clock with respect to the gate has
been resolved, a delay line is adjusted to match
the phases of the two signals.
There is a finite resolution to the phase detection
process (typically under 500ps), so that, from one
gate trigger to the next, there will remain some
residual gate-to-output jitter. However, for a given
gate, the jitter from one clock cycle to the next is
equal to the jitter of the reference clock itself.
The 3D6701 also contains a programmable
divider that reduces the output frequency by an
amount given by the D7:0 inputs. F_OUT is given by
F_IN / (D+1), so that the output frequency may
range from F_IN (D=0) to F_IN / 256 (D=255). When
G_IN returns low, the output returns to a low level
and remains there until the next rising edge of
G_IN.
The performance of CMOS integrated circuits is
strongly dependent on power supply stability. It is
essential that the power supply pins be
adequately bypassed and filtered. In addition, the
power bus should be of as low an impedance
construction as possible. Power planes are
preferred.
When operating at 3.3V, tie the SEL input to
GND. When operating at 5.0V, tie the SEL
input to VDD.
G_IN
Phase
Resolver
F_IN
Programmable
Delay Line
8-Bit
Divider
F_OUT
D7:0
Figure 2: 3D6701 Functional Block Diagram
DEVICE SPECIFICATIONS
TABLE 1: ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL MIN
MAX UNITS NOTES
DC Supply Voltage
Input Pin Voltage
Input Pin Current
Storage Temperature
Lead Temperature
V_DD
V_IN
I_IN
T_STRG
T_LEAD
-0.3
7.0
V
-0.3
V_DD+0.3
V
-1.0
1.0
mA
25C
-55
150
C
300
C
10 sec
Doc #14015
DATA DELAY DEVICES, INC.
2
6/9/2014
Tel: [phone] Fax: [phone] http://www.datadelay.com