3D6701 Datasheet, PDF (1/4 Pages) Data Delay Devices, Inc. – MONOLITHIC CLOCK SYNCHRONIZER (SERIES 3D6701)

MONOLITHIC CLOCK
SYNCHRONIZER
(SERIES 3D6701)
FEATURES
 Synchronizes free-running clock to external gate signal
 Input frequency range: 30MHz through 100MHz
 Phase resolution: 200ps typical
 Output frequency: Programmable from F_IN to F_IN/256
 Output period jitter: Equal to jitter of clock source
 All-silicon, low-power CMOS technology
 TTL/CMOS compatible inputs and outputs
 Vapor phase, IR and wave solderable
 Auto-insertable (DIP pkg.)
For mechanical dimensions, click here.
For package marking details, click here.
3D6701
PINOUT
VDD 1
F_OUT 2
D0 3
D2 4
D4 5
D6 6
G_IN 7
GND 8
16 VDD
15 SEL
14 D1
13 D3
12 D5
11 D7
10 FIN
9 GND
3D6701 DIP-14
3D6701D SOIC-14
FUNCTIONAL DESCRIPTION
One major drawback to using a crystal oscillator for frequency generation
is that the phase of the generated clock signal cannot be synchronized to
an external timing event. A delay-line oscillator (eg, the 3D7701), while
supporting this feature, cannot provide the stability and jitter performance
of a crystal. The 3D6701 clock synchronizer provides the best of both
worlds. The device accepts two inputs – a stable frequency source and a
gate signal – and matches the phase of the clock to the gate. It also
provides 8 bits of frequency scaling at the device output. The 3D6701
can be operated at 5V or 3.3V, and is offered in both a 16-pin DIP and a
space-saving 16-pin SOIC package.
PIN DESCRIPTIONS
F_IN Clock Input
G_IN Gate Input
D0-D7 Divisor Inputs
SEL VDD Select Input
F_OUT Sync Oscillator Out
VDD +3.3 or +5 Volts
GND Ground
FIN
(Async)
GIN
D_INH
OUT
(D=0)
OUT
(D=1)
OUT
(D=2)
Doc #14015
6/9/2014
T_RES
Figure 1: Timing Diagram
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
2014 Data Delay Devices
1