DS3181 Datasheet, PDF (90/400 Pages) Maxim Integrated Products – Single/Dual/Triple/Quad ATM/Packet PHYs with Built-In LIU

Figure 8-46. Clear Status Latched Register on Read
A[0]/BSWAP
A[10:1]
D[15:0]
CS
WR
RD
RDY
Z
0x1C0
0xFFFF
0x1C0
0x0000
Z
Z
DS3181/DS3182/DS3183/DS3184
Z
Figure 8-47. Clear Status Latched Register on Write
A[0]/BSWAP
A[10:1]
D[15:0]
CS
WR
RD
RDY
Z
0x1C0
0xFFFF
0x1C0
0x5555
Z
Z
0x1C0
0xAAAA
Z
Z
Z
Figure 8-48 and Figure 8-49 show exaggerated views of the Ready Signal to describe the difference in access
times to write or read to or from various memory locations on the DS318x device. Some registers will have a faster
access time than others will and if needed, the user can implement the RDY signal to maximize efficiency of read
and write accesses.
Figure 8-48. RDY Signal Functional Timing Writes
A[0]/BSWAP
A[10:1]
D[15:0]
CS
WR
RD
RDY
Z
0x2B0
0x1234
0x3A4
0x0078
Z
Z
Z
90