DS3181 Datasheet, PDF (193/400 Pages) Maxim Integrated Products – Single/Dual/Triple/Quad ATM/Packet PHYs with Built-In LIU

DS3181/DS3182/DS3183/DS3184
Note: Immediately after a reset (or datapath reset) or a LOS condition, a BPV will not be declared when the first
valid one (RPOS high and RNEG low, or RPOS low and RNEG high) is received. Bipolar to unipolar conversion
converts the AMI bipolar data into a unipolar signal by ORing together the RXP and RXN signals.
10.15 BERT
10.15.1 General Description
The BERT is a software-programmable test-pattern generator and monitor capable of meeting most error
performance requirements for digital transmission equipment. It will generate and synchronize to pseudo-random
patterns with a generation polynomial of the form xⁿ + x^y + 1, where n and y can take on values from 1 to 32 and to
repetitive patterns of any length up to 32 bits.
The transmit direction generates the programmable test pattern, and inserts the test pattern payload into the data
stream.
The receive direction extracts the test pattern payload from the receive data stream, and monitors the test pattern
payload for the programmable test pattern. Figure 10-54 shows the location of the BERT Block within the DS318x
devices.
Figure 10-54. BERT Block Diagram
DS3/E3
Transmit
LIU
DS3/E3
Receive
LIU
Clock Rate
Adapter
TAIS
TUA1
B3ZS/
HDB3
Encoder
DS3 / E3
Transmit
Formatter
Trail
FEAC Trace HDLC
Buffer
TX FRAC/
PLCP
B3ZS/
HDB3
Decoder
DS3 / E3
Receive
Framer
IEEE P1149.1
JTAG Test
Access Port
UA1
GEN
RX FRAC/
PLCP
Tx Cell
Processor
Tx Packet
Processor
TX BERT
RX BERT
Rx Packet
Processor
Rx Cell
Processor
Tx
FIFO
Rx
FIFO
Microprocessor
Interface
10.15.2 Features
• Programmable PRBS pattern – The Pseudo Random Bit Sequence (PRBS) polynomial (xⁿ + x^y + 1) and seed
are programmable (length n = 1 to 32, tap y = 1 to n - 1, and seed = 0 to 2ⁿ - 1).
• Programmable repetitive pattern – The repetitive pattern length and pattern are programmable (the length n
= 1 to 32 and pattern = 0 to 2ⁿ - 1).
• 24-bit error count and 32-bit bit count registers
• Programmable bit error insertion – Errors can be inserted individually, on a pin transition, or at a specific
rate. The rate 1/10ⁿ is programmable (n = 1 to 7).
• Pattern synchronization at a 10^-3 BER – Pattern synchronization will be achieved even in the presence of a
random Bit Error Rate (BER) of 10^-3.
10.15.3 Configuration and Monitoring
Set PORT.CR1.BENA = 1 to enable the BERT. The BERT must be enabled before the pattern is loaded for the
pattern load operation to take affect.
The following tables show how to configure the on-board BERT to send and receive common patterns.
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