DS3181 Datasheet, PDF (1/400 Pages) Maxim Integrated Products – Single/Dual/Triple/Quad ATM/Packet PHYs with Built-In LIU

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DS3181/DS3182/DS3183/DS3184
Single/Dual/Triple/Quad
ATM/Packet PHYs with Built-In LIU
GENERAL DESCRIPTION
The DS3181, DS3182, DS3183, and DS3184
(DS318x) integrate ATM cell/HDLC packet
processor(s) with a DS3/E3 framer(s) and LIU(s) to
map/demap ATM cells or packets into as many as
four DS3/E3 physical copper lines with DS3-framed,
E3-framed, or clear-channel data streams on per-port
basis.
APPLICATIONS
Access Concentrators Multiservice Access
SONET/SDH ADM
Platform (MSAP)
SONET/SDH Muxes Multiservice Protocol
PBXs
Platform (MSPP)
Digital Cross Connect ATM and Frame Relay
Test Equipment
Equipment
Routers and Switches PDH Multiplexer/
Integrated Access
Demultiplexer
Device (IAD)
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE
DS3181
DS3181N
DS3182
DS3182N
DS3183
DS3183N
DS3184
DS3184N
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
400 TE-PBGA (27mm x
27mm, 1.27mm pitch)
400 TE-PBGA (27mm x
27mm, 1.27mm pitch)
400 TE-PBGA (27mm x
27mm, 1.27mm pitch)
400 TE-PBGA (27mm x
27mm, 1.27mm pitch)
400 TE-PBGA (27mm x
27mm, 1.27mm pitch)
400 TE-PBGA (27mm x
27mm, 1.27mm pitch)
400 TE-PBGA (27mm x
27mm, 1.27mm pitch)
400 TE-PBGA (27mm x
27mm, 1.27mm pitch)
Note: Add the “+” suffix for the lead-free package option.
POS-PHY and POS-PHY Level 3 are trademarks of PMC-Sierra, Inc.
FUNCTIONAL DIAGRAM
DS3/E3/STS-1
PORTS
DS3/E3
CELL/
FRAMER/
PACKET
FORMATTER PROCESSOR
DS318x
POS-PHY
OR
UTOPIA
FEATURES
Single (DS3181), Dual (DS3182), Triple
(DS3183), or Quad (DS3184) with Integrated LIU
ATM/Packet PHYs for DS3, E3, and Clear-
Channel 52Mbps (CC52)
Pin Compatible for Ease of Port Density
Migration in the Same PC Board Platform
Each Port Independently Configurable
Perform Receive Clock/Data Recovery and
Transmit Waveshaping
Jitter Attenuator can be Placed Either in the
Receive or Transmit Paths
Interfaces to 75Ω Coaxial Cable at Lengths Up to
380 Meters or 1246 Feet (DS3) or 440 Meters or
1443 Feet (E3)
Uses 1:2 Transformers on Both Tx and Rx
Universal PHYs Map ATM Cells and/or HDLC
Packets into DS3 or E3 Data Streams
UTOPIA L2/L3 or POS-PHY™ L2/L3 or SPI-3
Interface with 8-, 16-, or 32-Bit Bus Width
66MHz UTOPIA L3 and POS-PHY L3 Clock
52MHz UTOPIA L2 and POS-PHY L2 Clock
Ports Independently Configurable for Cell or
Packet Traffic in POS-PHY Bus Modes
Direct, PLCP, DSS, and Clear-Channel Cell
Mapping
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 102406