DS1384 Datasheet, PDF (9/17 Pages) Dallas Semiconductor – Watchdog Timekeeping Controller

DS1384
TIME OF DAY ALARM REGISTERS
Registers 3, 5, and 7 contain the time of day alarm registers. Bits 3, 4, 5, and 6 of register 7 will always
read 0 regardless of how they are written. Bit 7 of registers 3, 5, and 7 are mask bits (Figure 3). When all
of the mask bits are logic 0, a time of day alarm will only occur when registers 2, 4, and 6 match the
values stored in registers 3, 5, and 7. An alarm will be generated every day when bit 7 of register 7 is set
to a logic 1. Similarly, an alarm is generated every hour when bit 7 of registers 7 and 5 is set to a logic 1.
When bit 7 of registers 7, 5, and 3 is set to a logic 1, an alarm will occur every minute when register 1
(seconds) rolls from 59 to 00.
Time of day alarm registers are written and read in the same format as the time of day registers. The time
of day alarm flag and interrupt is always cleared when alarm registers are read or written.
WATCHDOG ALARM REGISTERS
Registers C and D contain the time for the Watchdog Alarm. The two registers contain a time count from
00.01 to 99.99 seconds in BCD. The value written into the Watchdog Alarm Registers can be written or
read in any order. Any access to Register C or D will cause the Watchdog Alarm to reinitialize and clears
the Watchdog Flag Bit and the Watchdog Interrupt Output. When a new value is entered or the Watchdog
Registers are read, the Watchdog Timer will start counting down from the entered value to 0. When 0 is
reached, the Watchdog Interrupt Output will go to the active state. The Watchdog Timer Countdown is
interrupted and reinitialized back to the entered value every time either of the registers are accessed. In
this manner, controlled periodic accesses to the Watchdog Timer can prevent the Watchdog Alarm from
ever going to an active level. If access does not occur, countdown alarm will be repetitive. The
Watchdog Alarm Registers always read the entered value. The actual count down register is internal and
is not readable. Writing registers C and D to 0 will disable the Watchdog Alarm feature.
COMMAND REGISTER
Address location 0Bh is the Command Register where mask bits, control bits and flag bits reside. The
operation of each bit is as follows:
TE - Bit 7 Transfer enable - This bit when set to a logic 0 will disable the transfer of data between
internal and external clock registers. The contents in the external clock registers are now frozen and reads
or writes will not be affected with updates. This bit must be set to a logic 1 to allow updates.
IPSW - Bit 6 Interrupt switch - When set to a logic 1, INTA is the Time of Day Alarm and INTB /(INTB)
is the Watchdog Alarm. When set to logic 0, this bit reverses the output pins. INTA is now the Watchdog
Alarm output and INTB /(INTB) is the Time of Day Alarm output.
IBH/LO - Bit 5 Interrupt B Sink or Source Current -When this bit is set to a logic 1 and V_CC is applied,
INTB /(INTB) will source current (see DC characteristics I_OH). When this bit is set to a logic 0, INTB will
sink current (see DC characteristics I_OL).
PU/LVL - Bit 4 Interrupt pulse mode or level mode - This bit determines whether both interrupts will
output a pulse or level signal. When set to a logic 0, INTA and INTB /(INTB) will be in the level mode.
When this bit is set to a logic 1, the pulse mode is selected and INTA will sink current for a minimum of
3 ms and then release. INTB /(INTB) will either sink or source current, depending on the condition of bit
5, for a minimum of 3 ms and then release.
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