DS1384 Datasheet, PDF (8/17 Pages) Dallas Semiconductor – Watchdog Timekeeping Controller

DS1384
TIME OF DAY ALARM MASK BITS Figure 3
REGISTER
MINUTES HOURS DAYS
1
1
1 ALARM ONCE PER MINUTE
0
1
1 ALARM WHEN MINUTES MATCH
0
0
1 ALARM WHEN HOURS AND MINUTES MATCH
0
0
0 ALARM WHEN HOURS, MINUTES, AND DAYS MATCH
NOTE:
ANY OTHER BIT COMBINATIONS OF MASK BIT SETTINGS PRODUCE ILLOGICAL
OPERATION.
TIME OF DAY REGISTERS
Registers 0, 1, 2, 4, 6, 8, 9 and A contain time of day data in BCD. Ten bits within these eight registers
are not used and will always read 0 regardless of how they are written. Bits 6 and 7 in the Months
Register (9) are binary bits.
When set to logical 0, EOSC (bit 7) enables the real-time clock oscillator. This bit will normally be turned
on by the user during device initialization. However, the oscillator can be turned on and off as necessary
by setting this bit to the appropriate level.
Bit 6 of this same byte controls the square wave output (pin 24). When set to logical 0, the square wave
output pin will output a 1024 Hz square wave signal. When set to logic 1 the square wave output pin is in
a high impedance state.
Bit 6 of the Hours Register is defined as the 12- or 24-Hour Select Bit. When set to logic 1, the 12-hour
format is selected. In the 12-hour format, bit 5 is the AM/ PM bit with logical one being PM. In the 24-
hour mode, bit 5 is the second 10-hour bit (20-23 hours). The time of day registers are updated every 0.01
seconds from the real time clock, except when the TE bit (bit 7 of register B) is set low or the clock
oscillator is not running.
The preferred method of synchronizing data access to and from the Watchdog Timekeeper is to access the
Command Register by doing a write cycle to address location 0B and setting the TE bit (Transfer Enable
bit) to a logic 0. This will freeze the external time of day registers at the present recorded time allowing
access to occur without danger of simultaneous update. When the watch registers have been read or
written a second write cycle to location 0B, setting the TE bit to a logic 1, will put the time of day
registers back to being updated every 0.01 second. No time is lost in the real time clock because the
internal copy of the time of day register buffers are continually incremented while the external memory
registers are frozen. An alternate method of reading and writing the time of day registers is to ignore
synchronization. However, any single read may give erroneous data as the real time clock may be in the
process of updating the external memory registers as data is being read.
The internal copies of seconds through years are incremented and Time of Day Alarm is checked during
the period that hundredths of seconds reads 99 and are transferred to the external register when
hundredths of seconds roll from 99 to 00. A way of making sure data is valid is to do multiple reads and
compare. Writing the registers can also produce erroneous results for the same reasons. A way of making
sure that the write cycle has caused proper update is to do read verifies and re-execute the write cycle if
data is not correct. While the possibility of erroneous results from reads and write cycles has been stated,
it is worth noting that the probability of an incorrect result is kept to a minimum due to the redundant
structure of the Watchdog Timekeeper.
8 of 17