DS1384 Datasheet, PDF (4/17 Pages) Dallas Semiconductor – Watchdog Timekeeping Controller

DS1384
For more information on crystal selection and crystal layout considerations, please consult Application
Note 58, “Crystal Considerations with Dallas Real Time Clocks.”
SQW - Square Wave (output): This pin can be programmed to output a 1024 Hz square wave signal.
When the signal is turned off, the pin is high Z.
PFO - Power Fail Signal (output; active low when V_WP occurs): High state occurs t_REC after power-up and
V_CC >4.5 volts.
ADDRESS DECODING
The DS1384 accommodates 17 address lines, which allows direct connection of up to 128k bytes of static
RAM. The lower 14 bytes of RAM, regardless of the density used, will always contain the timekeeping,
alarm, and watchdog registers. The 14 clock registers reside in the lower 14 RAM locations without
conflict by inhibiting the OER (output enable RAM) signal during clock access. Since the watchdog
timekeeping chip actually contains 64 registers (14 RTC and 50 user RAM), the lower 64 bytes of any
attached memory resides within the DS1384. However, the RAM’s physical location is transparent to the
user and the memory map looks continuous from the first clock address to the upper most attached RAM
address.
OPERATION - READ CYCLE
The DS1384 executes a read cycle whenever WE is inactive (high) and CE and OE are active (low). The
unique address specified by the address inputs (A0-A16) defines which of the on-chip 64 RTC/RAM or
external SRAM locations is to be accessed. When the address value presented to the DS1384 is in the
range of 00000H through 0003FH, one of the 64 on-chip registers will be selected and valid data will be
available to the eight data output drivers within t_ACC (access time) after the address input signal is stable,
providing that the CE and OE access times are also satisfied. If they are not, then data access must be
measured from the latter occurring signal ( CE or OE ) and the limiting parameter is either t_CO for CE or
t_OE for OE rather than the address access time. When one of the on-chip registers is selected for read, the
OER signal will remain inactive throughout the read cycle.
When the address value presented to the DS1384 is in the range of 00040H through 1FFFFH, an external
SRAM location will be selected. In this case the OE signal will be passed to the OER pin, with the
specified delay times of t_AOEL or t_OERL.
OPERATION - WRITE CYCLE
The DS1384 is in the write mode whenever the WE (Write Enable) and CE (Chip Enable) signals are in
the active (low) state after the address inputs are stable. The latter occurring falling edge of CE or WE
will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE
or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state
for a minimum recovery state (t_WR) before another cycle can be initiated. Data must be valid on the data
bus with sufficient Data Set Up (t_DS) and Data Hold Time (t_DH) with respect to the earlier rising edge of
CE or WE . The OE control signal should be kept inactive (high) during write cycles to avoid bus
contention. However, if the output bus has been enabled ( CE and OE active), then WE will disable the
outputs in t_WEZ from its falling edge.
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