DS1384 Datasheet, PDF (16/17 Pages) Dallas Semiconductor – Watchdog Timekeeping Controller

DS1384
TIMING DIAGRAM: INTERRUPT OUTPUTS PULSE MODE (SEE NOTES 8, 9)
NOTES:
1. All voltages are referenced to ground.
2. Typical values are at 25°C and nominal supplies.
3. Outputs are open.
4. Value for voltage and currents is from the V_CCI input pin to the V_CCO pin.
5. Write protection trip point occurs during power fail prior to switchover from V_CC to V_BAT.
6. Value for voltage and currents is from the V_BAT input pin to the V_CCO pin.
7. Data retention time depends on the size of battery selected and the amount of current demanded by
the static RAM in back-up mode. The battery capacity (mA •=hr) to achieve a T_DR of 10 years is given
by the formula: C=(I_BAT1 + I_RAM) x 24 x 365 x 10, where I_RAM is the standby current of the static
RAM at the battery voltage. For the DS1384 chip alone, a standard 48 mAh lithium cell battery will
provide greater than 10 years of data retention in the absence of power.
8. Applies to both interrupt pins when the alarms are set to pulse.
9. Interrupt output occurs within 100 ns of the alarm condition existing.
OUTPUT LOAD
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