DS1682_13 Datasheet, PDF (8/14 Pages) Dallas Semiconductor – Total-Elapsed-Time Recorder with Alarm

CONFIGURATION REGISTER
DS1682 Total-Elapsed-Time Recorder with Alarm
MSB
BIT 7
0
BIT 6
AF
BIT 5
WDF
BIT 4
WMDF
BIT 3
AOS
BIT 2
RE
BIT 1
AP
LSB
BIT 0
ECMSB
Note: The configuration register is not stored in EEPROM until an event becomes inactive. RE does not need to be
stored in EEPROM to reset the device.
Bit 6: Alarm Flag (AF). The alarm flag is set to a 1 when the ETC value matches the alarm register.
Once the AF bit is set to a 1, it cannot be set to a 0. This bit is read-only.
Bit 5: Write Disable Flag (WDF). When the write disable command is written to AAh twice at memory
location 1Eh, the WDF is set to a 1 and cannot be cleared or reset. When WDF is set to a 1, the alarm,
ETC, and event counter registers are read-only. This bit is read-only. The writes need not be consecutive.
Cycling power on V_CC prior to the second write terminates the reset sequence.
Bit 4: Write-Memory-Disable Flag (WMDF). When the write-memory-disable command is written to
F0h twice at memory location 1Fh, the WMDF is set to a 1 and cannot be reset or cleared. Once the
WMDF is set to a 1, the 10-byte user memory becomes read-only. This bit is read-only. The writes need
not be consecutive. Cycling power on V_CC prior to the second write terminates the reset sequence.
Bit 3: Alarm Output Select (AOS). If AOS is 0 and AF is true, the DS1682 activates the ALARM
output during an event when AF becomes true. The DS1682 also activates the ALARM output by pulling
the pin low four times at power-up, at the start and end of an event, or when the ALARM pin is pulled
low and released. This output mode can be used to flash an LED or to communicate with another device
to indicate that an alarm has occurred. AP has no affect on the output when AOS is 0.
If AOS is a 1 and AF is true, the ALARM output is constant when the alarm is active. AP determines the
polarity of the output.
Bit 2: Reset Enable (RE). The reset enable bit allows the device to be reset by enabling the reset
command. The sections of the DS1682 that are reset are then dependent on the value in the WDF. With
the WDF set to 0 and the reset enable bit set to a 1, the reset command clears the ETC, EEPROM, and
event counter. When the reset enable bit is set to a 0, the reset command is disabled.
Bit 1: Alarm Polarity (AP). When the alarm polarity bit in the configuration register is set to 0, the
ALARM output is high impedance during the period that the value in the ETC is less than the alarm
register value. When the ETC matches the alarm value, the ALARM pin is driven low. If the AP bit is set
to a 1, the ALARM output is driven low during the period that the ETC is less than the alarm value.
When the ETC matches the alarm value, the ALARM pin becomes high impedance. The AP bit has no
affect if AOS is set to a 0.
Bit 0: Event Counter MSB (ECMSB). This bit is read-only.
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