DS1682_13 Datasheet, PDF (10/14 Pages) Dallas Semiconductor – Total-Elapsed-Time Recorder with Alarm

DS1682 Total-Elapsed-Time Recorder with Alarm
generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the
slave must leave the data line high to enable the master to generate the STOP condition.
Depending upon the state of the R/W bit, two types of data transfer are possible:
Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is
the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each
received byte.
Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the
slave address). The slave then returns an acknowledge bit. Next follows a number of data bytes
transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes
other than the last byte. A “not acknowledge” is returned at the end of the last received byte.
The master device generates all of the serial clock pulses and the START and STOP conditions. A
transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START
condition is also the beginning of the next serial transfer, the bus is not released.
Figure 6. Timing Diagram: Data Transfer on 2-Wire Serial Bus
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