DS1682_13 Datasheet, PDF (14/14 Pages) Dallas Semiconductor – Total-Elapsed-Time Recorder with Alarm

TIMING DIAGRAM
DS1682 Total-Elapsed-Time Recorder with Alarm
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Typical values are at +25°C, V_CC = 4.0V.
The elapsed time and event counters are backed by three EEPROM arrays, which are used
sequentially, allowing up to 3 x E_E. The configuration register, alarm trip-point register and user
memory use a single array, limiting them to one E_E.
A decoupling capacitor to supply high instantaneous currents during EEPROM writes is recommended.
A typical value is 0.01μF. V_CC must be maintained above V_CC minimum, including transients, during
EEPROM writes.
V_CC must be at or above 2.5V for t_EW after the end of an event to ensure data transfer to the EEPROM.
Reading data while the contents of EEPROM are transferred to RAM results in incorrect reads.
After this period, the first clock pulse is generated.
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the
V_IHMIN of the SCL signal) to bridge the undefined region of the falling edge of SCL.
The maximum t_HD:DAT has only to be met if the device does not stretch the low period (t_LOW) of the SCL
signal.
A fast-mode device can be used in a standard-mode system, but the requirement t_SU:DAT ≥ 250ns must
be met. This is automatically the case if the device does not stretch the t_LOW. If such a device does
stretch t_LOW, it must output the next data bit to the SDA line t_R(MAX) + t_SU:DAT = 1000 + 250 = 1250ns
before the SCL line is released.
C_B—total capacitance of one bus line in pF.
CHIP INFORMATION
TRANSISTOR COUNT: 26,032
PROCESS: CMOS
PACKAGE INFORMATION
For the latest package information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
8 SO
S8+5
21-0041
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