DS1682_13 Datasheet, PDF (7/14 Pages) Dallas Semiconductor – Total-Elapsed-Time Recorder with Alarm

DS1682 Total-Elapsed-Time Recorder with Alarm
ALARM
The alarm register is a 32-bit register that holds time in quarter-second resolution. When a nonzero
number is programmed into the alarm register, the ALARM function is enabled and the DS1682 monitors
the values in the ETC for the programmed value in the alarm register. When the ETC matches the alarm
value, the alarm flag is set.
EEPROM ARRAY
When power is applied, the contents of the EEPROM are transferred to the configuration register, alarm
register, ETC, event counter, and user memory. When the event pin goes low, V_CC must remain above
V_CC minimum for t_EW to ensure the EEPROM is properly written.
The EEPROM array for the ETC and the event counter is made up of three banks. Each bank can be
written a maximum of 50k times. The device switches between banks based upon the value in the event
counter. Resetting the event counter before the counter reaches 50,000 will cause additional writes to the
first bank, which can allow writes in excess of 50k. If the event counter is set to greater than 50k or 100k
prior to reset, the device stays on the selected bank. This could result in writes in excess of 50k to one
bank.
The configuration and alarm registers and the user memory are held in one bank of EEPROM. Writes at
the end of an event only occur if the data has changed in one or more of those registers.
User-modified data in any of the registers is stored in EEPROM only if the data was written while an
event was active and is stored when the event ends.
EVENT COUNTER REGISTER
This 17-bit event counter register set provides the total number of data samples logged during the life of
the product up to 131,072 separate events. The event counter consists of 2 bytes of memory in the
memory map plus the event counter MSB bit (ECMSB) in the configuration register. Once the event
counter reaches 1FFFFh, event counting stops.
RESET COMMAND
If RE is set to a 1, a reset occurs when a reset command is sent through the 2-wire bus. A reset command
is issued by writing 55h twice into memory location 1Dh. The writes need not be consecutive. Cycling
power on V_CC prior to the second write terminates the reset sequence.
Upon reset, the ETC and event counter registers are cleared. The AF, RE, and ECMSB bits are cleared by
the device, and the configuration register becomes read-only. The data are written to the EEPROM, and
additional resets are ignored.
When a reset command is issued, no additional command should be issued during the EEPROM write
time (t_EW).
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