DS1086 Datasheet, PDF (8/14 Pages) Dallas Semiconductor – DS1086 Spread-Spectrum EconOscillator

DS1086 Spread-Spectrum EconOscillator
Table 1. Register Summary
REGISTER ADDR MSB
BINARY
PRESCALER 02h
X₁
X₁
X_X
J0
P3
DAC HIGH
08h
b9
b8 b7 b6 b5
DAC LOW
OFFSET
ADDR
RANGE
WRITE EE
09h
b1
b0
X₀
X₀
X₀
0Eh
X₁
X₁
X₁
b4
b3
0Dh
X₁
X₁
X₁
X₁ WC
37h
X_X
X_X
X_X
b4
b3
3Fh
NO DATA
X₀ = Don’t care, reads as zero.
X₁ = Don’t care, reads as one.
X_X = Don’t care, reads indeterminate.
X = Don’t care.
Table 2. Offset Settings
OFFSET
OS - 6
OS - 5
OS - 4
OS - 3
OS - 2
OS - 1
OS*
OS + 1
OS + 2
OS + 3
OS + 4
OS + 5
OS + 6
FREQUENCY RANGE (MHz)
61.44 to 71.67
66.56 to 76.79
71.68 to 81.91
76.80 to 87.03
81.92 to 92.15
87.04 to 97.27
92.16 to 102.39
97.28 to 107.51
102.40 to 112.63
107.52 to 117.75
112.64 to 122.87
117.76 to 127.99
122.88 to 133.11
*Factory default setting. OS is the integer value of the 5 LSBs
of the RANGE register.
Detailed Description
A block diagram of the DS1086 is shown in Figure 3.
The internal master oscillator generates a square wave
with a 66MHz to 133MHz frequency range. The fre-
quency of the master oscillator can be programmed
with the DAC register over a two-to-one range in 10kHz
steps. The master oscillator range is larger than the
range possible with the DAC step size, so the OFFSET
register is used to select a smaller range of frequencies
over which the DAC spans. The prescaler can then be
set to divide the master oscillator frequency by 2^x
LSB
P2 P1 P0
b4 b3 b2
X₀
X₀
X₀
b2 b1 b0
A2 A1 A0
b2 b1 b0
FACTORY
DEFAULT
11100000b
01111101b
00000000b
111-----b
11110000b
xxx-----b
—
ACCESS
R/W
R/W
R/W
R/W
R/W
R
—
(where x equals 0 to 8) before routing the signal to the
output (OUT) pin.
A programmable triangle-wave generator injects an off-
set element into the master oscillator to dither its output
2% or 4%. The dither is controlled by the J0 bit in the
PRESCALER register and enabled with the SPRD pin.
The maximum spectral attenuation occurs when the
prescaler is set to 1. The spectral attenuation is
reduced by 2.7dB for every factor of 2 that is used in
the prescaler. This happens because the prescaler’s
divider function tends to average the dither in creating
the lower frequency. However, the most stringent spec-
tral emission limits are imposed on the higher frequen-
cies where the prescaler is set to a low divider ratio.
The external control input, OE, gates the clock output
buffer. The PDN pin disables the master oscillator and
turns off the clock output for power-sensitive applica-
tions*. On power-up, the clock output is disabled until
power is stable and the master oscillator has generated
512 clock cycles. Both controls feature a synchronous
enable that ensures there are no output glitches when
the output is enabled, and a constant time interval (for a
given frequency setting) from an enable signal to the
first output transition.
The control registers are programmed through a 2-wire
interface and are used to determine the output frequen-
cy and settings. Once programmed into EEPROM,
since the register settings are NV, the settings only
need to be reprogrammed if it is desired to reconfigure
the device.
*The power-down command must persist for at least two out-
put frequency cycles plus 10µs for deglitching purposes.
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