DS1086 Datasheet, PDF (12/14 Pages) Dallas Semiconductor – DS1086 Spread-Spectrum EconOscillator

DS1086 Spread-Spectrum EconOscillator
MSB
1
0
1
DEVICE
IDENTIFIER
LSB
1
A2
A1
A0 R/W
DEVICE
ADDRESS
Figure 5. Slave Address
SDA
t_BUF
t_LOW
t_R
t_F
t_HD:STA
t_SP
SCL
STOP START
t_HD:STA
Figure 6. 2-Wire AC Characteristics
t_HD:DAT
t_HIGH
t_SU:DAT
t_SU:STA
REPEATED
START
t_SU:STO
Since the expected output frequency is equal to the
desired frequency, the calculated error is 0%.
_______2-Wire Serial Port Operation
2-WIRE SERIAL DATA BUS
The DS1086 communicates through a 2-wire serial
interface. A device that sends data onto the bus is
defined as a transmitter, and a device receiving data
as a receiver. The device that controls the message is
called a "master." The devices that are controlled by the
master are "slaves." A master device that generates the
serial clock (SCL), controls the bus access, and gener-
ates the START and STOP conditions must control the
bus. The DS1086 operates as a slave on the 2-wire
bus. Connections to the bus are made through the
open-drain I/O lines SDA and SCL.
The following bus protocol has been defined (see
Figures 4 and 6):
• Data transfer can be initiated only when the bus is
not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is high are
interpreted as control signals.
Accordingly, the following bus conditions have been
defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data
line, from HIGH to LOW, while the clock is HIGH,
defines a START condition.
Stop data transfer: A change in the state of the data
line, from LOW to HIGH, while the clock line is HIGH,
defines the STOP condition.
Data valid: The state of the data line represents valid
data when, after a START condition, the data line is sta-
ble for the duration of the HIGH period of the clock sig-
nal. The data on the line must be changed during the
LOW period of the clock signal. There is one clock
pulse per bit of data.
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