DS1556 Datasheet, PDF (6/20 Pages) Dallas Semiconductor – 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM

DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM
Table 2. Register Map
ADDRESS
1FFFFh
1FFFEh
1FFFDh
1FFFCh
1FFFBh
1FFFAh
1FFF9h
1FFF8h
1FFF7h
1FFF6h
1FFF5h
1FFF4h
1FFF3h
1FFF2h
1FFF1h
1FFF0h
DATA
B₇
B₆
B₅
B₄
B₃
B₂
B₁
B₀
10 Year
Year
X
X
X
10
Month
Month
X
X
10 Date
Date
X
Ft
X
X
X
Day
X
X
10 Hour
Hour
X
10 Minutes
OSC
10 Seconds
Minutes
Seconds
W
R
10 Century
Century
WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0
AE
Y
ABE
Y
Y
Y
Y
Y
AM4
Y
10 Date
Date
AM3
Y
10 Hours
Hours
AM2
10 Minutes
Minutes
AM1
10 Seconds
Seconds
Y
Y
Y
Y
Y
Y
Y
Y
WF
AF
0
BLF
0
0
0
0
FUNCTION
Year
Month
Date
Day
Hour
Minutes
Seconds
Control
Watchdog
Interrupts
Alarm Date
Alarm Hours
Alarm Minutes
Alarm Seconds
Unused
Flags
X = Unused, Read/Writable Under Write and Read Bit Control
Y = Unused, Read/Writable Without Write and Read Bit Control
FT = Frequency Test Bit
OSC = Oscillator Start/Stop Bit
W = Write Bit
R = Read Bit
WDS = Watchdog Steering Bit
BMB0 to BMB4 = Watchdog Multiplier Bits
AE = Alarm Flag Enable
ABE = Alarm in Battery-Backup Mode Enable
AM1 to AM4 = Alarm Mask Bits
WF = Watchdog Flag
AF = Alarm Flag
0 = 0 (Read Only)
BLF = Battery Low Flag
RB0 to RB1 = Watchdog Resolution Bits
RANGE
00-99
01-12
01-31
01-07
00-23
00-59
00-59
00-39
01-31
00-23
00-59
00-59
CLOCK OSCILLATOR CONTROL
The clock oscillator can be stopped at any time. To increase the shelf life of the backup lithium battery
source, the oscillator can be turned off to minimize current drain from the battery. The OSC bit is the
MSB of the Seconds Register (B7 of 1FFF9h). Setting it to a 1 stops the oscillator, setting to a 0 starts the
oscillator. The DS1556 is shipped from Dallas Semiconductor with the clock oscillator turned off, OSC
bit set to a 1.
READING THE CLOCK
When reading the RTC data, it is recommended to halt updates to the external set of double-buffered RTC
Registers. This puts the external registers into a static state allowing data to be read without register
values changing during the read process. Normal updates to the internal registers continue while in this
state. External updates are halted when a 1 is written into the read bit, B6 of the Control Register
(1FFF8h). As long as a 1 remains in the Control Register read bit, updating is halted. After a halt is
issued, the registers reflect the RTC count (day, date, and time) that was current at the moment the halt
command was issued. Normal updates to the external set of registers will resume within 1 second after the
read bit is set to a 0 for a minimum of 500 ms. The read bit must be a zero for a minimum of 500 ms to
ensure the external registers will be updated.
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