DS1556 Datasheet, PDF (4/20 Pages) Dallas Semiconductor – 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM

DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM
Table 1. Operating Modes
V_CC
CE OE WE
V_IH X X
V_CC > V_PF
V_IL X V_IL
V_IL V_IL V_IH
V_IL V_IH V_IH
V_SO < V_CC <V_PF X X X
V_CC <V_SO < V_PF X X X
DQ0–DQ7
High-Z
D_IN
D_OUT
High-Z
High-Z
High-Z
MODE
Deselect
Write
Read
Read
Deselect
Data Retention
POWER
Standby
Active
Active
Active
CMOS Standby
Battery Current
DATA-READ MODE
The DS1556 is in the read mode whenever CE (chip enable) is low and WE (write enable) is high. The
device architecture allows ripple-through access to any valid address location. Valid data will be available
at the DQ pins within t_AA after the last address input is stable, providing that CE and OE access times are
satisfied. If CE or OE access times are not met, valid data will be available at the latter of chip enable
access (t_CEA) or at output enable access time (t_OEA). The state of the data input/output pins (DQ) is
controlled by CE and OE. If the outputs are activated before t_AA, the data lines are driven to an
intermediate state until t_AA. If the address inputs are changed while CE and OE remain valid, output data
will remain valid for output data hold time (tOH) but will then go indeterminate until the next address
access.
DATA-WRITE MODE
The DS1556 is in the write mode whenever WE and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE or CE. The addresses must be held valid throughout the
cycle. CE and WE must return inactive for a minimum of t_WR prior to the initiation of a subsequent read
or write cycle. Data in must be valid tDS prior to the end of the write and remain valid for t_DH afterward. In
a typical application, the OE signal will be high during a write cycle. However, OE can be active
provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE
transitioning low, the data bus can become active with read data defined by the address inputs. A low
transition on WE will then disable the outputs t_WEZ after WE goes active.
DATA-RETENTION MODE
The 5V device is fully accessible and data can be written and read only when V_CC is greater than V_PF.
However, when V_CC is below the power-fail point V_PF (point at which write protection occurs) the
internal clock registers and SRAM are blocked from any access. When V_CC falls below the battery switch
point V_SO (battery supply level), device power is switched from the V_CC pin to the internal backup lithium
battery. RTC operation and SRAM data are maintained from the battery until V_CC is returned to nominal
levels.
The 3.3V device is fully accessible and data can be written and read only when V_CC is greater than V_PF.
hen V_CC falls below V_PF, access to the device is inhibited. If V_PF is less than V_SO, the device power is
switched from V_CC to the internal backup lithium battery when V_CC drops below V_PF. If V_PF is greater
than V_SO, the device power is switched from V_CC to the internal backup lithium battery when V_CC drops
below V_SO. RTC operation and SRAM data are maintained from the battery until V_CC is returned to
nominal levels.
All control, data, and address signals must be powered down when V_CC is powered down.
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