DS1646 Datasheet, PDF (5/11 Pages) Dallas Semiconductor – Nonvolatile Timekeeping RAM

WRITING DATA TO RAM OR CLOCK
DS1646/DS1646P
The DS1646 is in the write mode whenever WE and CE are in their active state. The start of a write is
referenced to the latter occurring high to low transition of WE and CE . The addresses must be held valid
throughout the cycle. CE or WE must return inactive for a minimum of t_WR prior to the initiation of
another read or write cycle. Data in must be valid t_DS prior to the end of write and remain valid for t_DH
afterward. In a typical application, the OE signal will be high during a write cycle. However, OE can be
active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE
transitioning low the data bus can become active with read data defined by the address inputs. A low
transition on WE will then disable the outputs t_WEZ after WE goes active.
DATA RETENTION MODE
When V_CC is within nominal limits (V_CC > 4.5 volts) the DS1646 can be accessed as described above with
read or write cycles. However, when V_CC is below the power-fail point V_PF (point at which write
protection occurs) the internal clock registers and RAM are blocked from access. This is accomplished
internally by inhibiting access via the CE signal. At this time the power-fail output signal ( PFO ) will be
driven active low and will remain active until V_CC returns to nominal levels. When V_CC falls below the
level of the internal battery supply, power input is switched from the V_CC pin to the internal battery and
clock activity, RAM, and clock data are maintained from the battery until V_CC is returned to nominal
level.
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