DS1646 Datasheet, PDF (3/11 Pages) Dallas Semiconductor – Nonvolatile Timekeeping RAM

BLOCK DIAGRAM DS1646 Figure 1
DS1646/DS1646P
TRUTH TABLE DS1646 Table 1
V_CC
CE
OE WE
V_IH
X
X
X
X
X
5V ± 10%
<4.5V >V_BAT
<V_BAT
V_IL
X
V_IL
V_IL
V_IL
V_IH
V_IL
V_IH
V_IH
X
X
X
X
X
X
MODE
DESELECT
DESELECT
WRITE
READ
READ
DESELECT
DESELECT
DQ
HIGH-Z
HIGH-Z
DATA IN
DATA OUT
HIGH-Z
HIGH-Z
HIGH-Z
POWER
STANDBY
STANDBY
ACTIVE
ACTIVE
ACTIVE
CMOS STANDBY
DATA RETENTION
MODE
SETTING THE CLOCK
The MSB Bit, B7, of the control register is the write bit. Setting the write bit to a 1, like the read bit halts
updates to the DS1646 registers. The user can then load them with the correct day, date and time data in
24-hour BCD format. Resetting the write bit to a 0 then transfers those values to the actual clock counters
and allows normal operation to resume.
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off
to minimize current drain from the battery. The OSC bit is the MSB for the second’s registers. Setting it
to a 1 stops the oscillator.
FREQUENCY TEST BIT
Bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to logic 1 and
the oscillator is running, the LSB of the second’s register will toggle at 512 Hz. When the seconds
register is being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for access
remain valid (i.e., CE low, OE low, and address for seconds register remain valid and stable).
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