DS14285 Datasheet, PDF (5/25 Pages) Dallas Semiconductor – Real Time Clock with NV RAM Control

DS14285/DS14287
In a typical application RESET can be connected to V_CC. This connection will allow the DS14287 to go in
and out of power fail without affecting any of the control registers.
CEI (External RAM Chip Enable Input, active low) - CEI should be driven low to enable the external
RAM. CEI is internally pulled up with a 50kΩ resistor.
CEO (External RAM Chip Enable Output, active low) - When V_CC is greater than 4.25 volts (typical),
CEO will reflect CEI provided the RESET is at a logic high. When V_CC is less than 4.25 volts (typical),
CEO will be forced to an inactive level regardless of CEI .
V_CCO (External RAM Power Supply Output) - V_CCO provides the higher of V_CC or V_BAT through an
internal switch to power an external RAM.
DS14285 Only
X1, X2 - Connections for a standard 32.768 kHz quartz crystal. The internal oscillator circuitry is
designed for operation with a crystal having a specified load capacitance (CL) of 6 pF. The crystal is
connected directly to the X1 and X2 pins. There is no need for external capacitors or resistors. Note: X1
and X2 are very high impedance nodes. It is recommended that they and the crystal be guard–ringed with
ground and that high frequency signals be kept away from the crystal area. For more information on
crystal selection and crystal layout considerations, please consult Application Note 58, “Crystal
Considerations with Dallas Real Time Clocks.”
V_BAT – Battery input for any standard 3-volt lithium cell or other energy source. See the Power-Up/Down
section for considerations in selecting the size of the external energy source
The battery should be connected directly to the V_BAT pin. A diode must not be placed in series with the
battery to the VBAT pin. Furthermore, a diode is not necessary because reverse charging current
protection circuitry is provided internal to the device and has passed the requirements of Underwriters
Laboratories for UL listing.
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