DS14285 Datasheet, PDF (13/25 Pages) Dallas Semiconductor – Real Time Clock with NV RAM Control

DS14285/DS14287
NONVOLATILE RAM
The 114 general purpose nonvolatile RAM bytes are not dedicated to any special function within the
DS14285/DS14287. They can be used by the processor program as nonvolatile memory and are fully
available during the update cycle.
The DS14285/DS14287 can also provide additional nonvolatile RAM. This is accomplished through the
use of its internal lithium cell in the case of the DS14287 (or the energy source connected to the V_BAT pin
in the case of the DS14285) and battery-backup controller to make a standard CMOS SRAM nonvolatile
during power-fail conditions. During power-fail, the DS14285/DS14287 automatically write-protects the
external SRAM and provides a V_CC output sourced from the internal lithium cell. The interface between
the DS14285/DS14287 and an external SRAM is illustrated in Figure 3.
EXTERNAL SRAM INTERFACE TO THE DS14285/DS14287 RTC Figure 3
INTERRUPTS
The RTC plus RAM includes three separate, fully automatic sources of interrupt for a processor. The
alarm interrupt can be programmed to occur at rates from once per second to once per day. The periodic
interrupt can be selected for rates from 500 ms to 122 µs. The update-ended interrupt can be used to
indicate to the program that an update cycle is complete. Each of these independent interrupt conditions is
described in greater detail in other sections of this text.
The processor program can select which interrupts, if any, are going to be used. Three bits in Register B
enable the interrupts. Writing a logic 1 to an interrupt-enable bit permits that interrupt to be initiated when
the event occurs. A 0 in an interrupt-enable bit prohibits the IRQ pin from being asserted from that
interrupt condition. If an interrupt flag is already set when an interrupt is enabled, IRQ is immediately set
at an active level, although the interrupt initiating the event may have occurred much earlier. As a result,
there are cases where the program should clear such earlier initiated interrupts before first enabling new
interrupts. When an interrupt event occurs, the relating flag bit is set to logic 1 in Register C. These flag
bits are set independent of the state of the corresponding enable bit in Register B. The flag bit can be used
in a polling mode without enabling the corresponding enable bits. The interrupt flag bit is a status bit
which software can interrogate as necessary. When a flag is set, an indication is given to software that an
interrupt event has occurred since the flag bit was last read; however, care should be taken when using the
flag bits as they are cleared each time Register C is read. Double latching is included with Register C so
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