DS14285 Datasheet, PDF (3/25 Pages) Dallas Semiconductor – Real Time Clock with NV RAM Control

DS14285/DS14287
For the DS14287 the internal lithium cell is electrically isolated from the clock and memory when
shipped from the factory. This isolation is removed after the first application of V_CC, allowing the lithium
cell to provide data retention to the clock, internal RAM, V_CCO and CEO on subsequent power-downs.
Care must be taken after this isolation has been broken to avoid inadvertently discharging the lithium cell
through the V_CCO and CEO pins.
OPERATION
The block diagram in Figure 1 shows the pin connections with the major internal functions of the
DS14285/DS14287. The following paragraphs describe the function of each pin.
SIGNAL DESCRIPTIONS
GND, V_CC - DC power is provided to the device on these pins. V_CC is the +5 volt input.
SQW (Square Wave Output) - The SQW pin can output a signal from one of 13 taps provided by the 15
internal divider stages of the real time clock. The frequency of the SQW pin can be changed by
programming Register A as shown in Table 1. The SQW signal can be turned on and off using the SQWE
bit in Register B. The SQW signal is not available when V_CC is less than 4.25 volts typical.
AD0-AD7 (Multiplexed Bi-directional Address/Data Bus) - Multiplexed buses save pins because
address information and data information time-share the same signal paths. The addresses are present
during the first portion of the bus cycle and the same pins and signal paths are used for data in the second
portion of the cycle. Address/data multiplexing does not slow the access time of the DS14285/DS14287
since the bus change from address to data occurs during the internal RAM access time. Addresses must be
valid prior to the falling edge of AS/ALE, at which time the DS14285/DS14287 latches the address from
AD0 to AD6. Valid write data must be present and held stable during the latter portion of the DS or WR
pulses. In a read cycle the DS14285/DS14287 outputs 8 bits of data during the latter portion of the DS or
RD pulses. The read cycle is terminated and the bus returns to a high impedance state as DS transitions
low in the case of Motorola timing or as RD transitions high in the case of Intel timing.
MOT (Mode Select) - The MOT pin offers the flexibility to choose between to bus types. When
connected to V_CC, Motorola bus timing is selected. When connected to GND or left disconnected, Intel
bus timing is selected. The pin has an internal pull-down resistance of approximately 20 KΩ. This pin is
on the DS14285Q only.
AS (Address Strobe Input) - A positive going address strobe pulse serves to demultiplex the bus. The
falling edge of AS/ALE causes the address to be latched within the DS14285/DS14287.
DS (Data Strobe or Read Input) - For the DS14285Q the DS/ RD pin has two modes of operation
depending on the level of the MOT pin. When the MOT pin is connected to V_CC, Motorola bus timing is
selected. In this mode DS is a positive pulse during the latter portion of the bus cycle and is called Data
Strobe. During read cycles, DS signifies the time that the DS14285Q is to drive the bidirectional bus. In
write cycles the trailing edge of DS causes the DS14285Q to latch the written data. When the MOT pin is
connected to GND, Intel bus timing is selected. In this mode the DS pin is called Read( RD ). RD identifies
the time period when the DS14285Q drives the bus with read data. The RD signal is the same definition
as the Output Enable ( OE ) signal on a typical memory.
The DS14285, DS14285S and DS14287 do not have a MOT pin and therefore operate only in Intel bus
timing mode.
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