DS1743 Datasheet, PDF (4/17 Pages) Dallas Semiconductor – Y2KC Nonvolatile Timekeeping RAM

DS1743/DS1743P
CLOCK ACCURACY (DIP MODULE)
The DS1743 is guaranteed to keep time accuracy to within ±1 minute per month at 25°C. The RTC is
calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements, and does not require
additional For this reason, methods of field clock calibration are not available and not necessary. Clock
accuracy is also effected by the electrical environment and caution should be taken to place the RTC in the
lowest level EMI section of the PCB layout. For additional information please see application note 58.
CLOCK ACCURACY (POWERCAP MODULE)
The DS1743 and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module will typically keep time accuracy to within ±1.53 minutes per month (35 ppm) at 25°C. Clock
accuracy is also effected by the electrical environment and caution should be taken to place the RTC in the
lowest level EMI section of the PCB layout. For additional information please see application note 58.
DS1743 REGISTER MAP Table 2
ADDRESS
B₇
1FFF
B₆
B₅
10 Year
DATA
B₄
B₃
1FFE
X
X
X 10 Mo
1FFD
X
X
10 Date
1FFC
BF
FT
X
X
X
1FFB
X
X
10 HOUR
1FFA
X
10 MINUTES
1FF9
OSC
10 SECONDS
1FF8
W
R
10 CENTURY
B₂
B₁
YEAR
MONTH
DATE
DAY
HOUR
MINUTES
SECONDS
CENTURY
OSC = STOP BIT
W = WRITE BIT
R = READ BIT
X = SEE NOTE BELOW
FUNCTION/RANGE
B₀
YEAR
00-99
MONTH
01-12
DATE
01-31
DAY
01-07
HOUR
00-23
MINUTES
00-59
SECONDS
00-59
CONTROL
00-39
FT = FREQUENCY TEST
BF = BATTERY FLAG
NOTE:
All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1743 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and CE
(chip enable) is low. The device architecture allows ripple-through access to any of the address locations
in the NV SRAM. Valid data will be available at the DQ pins within t_AA after the last address input is
stable, providing that the CE , and OE access times and states are satisfied. If CE , or OE access times and
states are not met, valid data will be available at the latter of chip enable access (t_CEA) or at output enable
access time (t_CEA). The state of the data input/output pins (DQ) is controlled by CE , and OE . If the
outputs are activated before t_AA, the data lines are driven to an intermediate state until t_AA. If the address
inputs are changed while CE , and OE remain valid, output data will remain valid for output data hold time
(t_OH) but will then go indeterminate until the next address access.
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