DS1743 Datasheet, PDF (3/17 Pages) Dallas Semiconductor – Y2KC Nonvolatile Timekeeping RAM

DS1743 BLOCK DIAGRAM Figure 1
DS1743/DS1743P
DS1743 TRUTH TABLE Table 1
V_CC
V_CC>V_PF
V_SO<V_CC<V_PF
V_CC<V_SO<V_PF
CE CE2 OE WE
V_IH X X X
X V_IL X X
V_IL V_IH X V_IL
V_IL V_IH V_IL V_IH
V_IL V_IH V_IH V_IH
X XXX
X XXX
MODE
DESELECT
DESELECT
WRITE
READ
READ
DESELECT
DESELECT
DQ
HIGH-Z
HIGH-Z
DATA IN
DATA OUT
HIGH-Z
HIGH-Z
HIGH-Z
POWER
STANDBY
STANDBY
ACTIVE
ACTIVE
ACTIVE
CMOS STANDBY
DATA RETENTION
MODE
SETTING THE CLOCK
As shown in Table 2, bit 7 of the century register is the write bit. Setting the write bit to a 1, like the read
bit, halts updates to the DS1743 registers. The user can then load them with the correct day, date and time
data in 24-hour BCD format. Resetting the write bit to a 0 then transfers those values to the actual clock
counters and allows normal operation to resume.
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off
to minimize current drain from the battery. The OSC bit is the MSB (bit 7) of the seconds registers, see
Table 2. Setting it to a 1 stops the oscillator.
FREQUENCY TEST BIT
As shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to
logic 1 and the oscillator is running, the LSB of the seconds register will toggle at 512 Hz. When the
seconds register is being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for
access remain valid (i.e., CE low, OE low, WE high, and address for seconds register remain valid and
stable).
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