DS1710 Datasheet, PDF (3/14 Pages) Dallas Semiconductor – Partitioned NV Controller

DS1710
read cycle after power-up to any location in memory, verifying that memory location’s contents. A
subsequent write cycle can then be executed to the same memory location altering the data. If the next
read cycle fails to verify the written data then the data is in danger of being corrupted. The fifth function
of the DS1710 provides for battery redundancy. When data integrity is extremely important it is wise to
use two batteries to insure reliability. The DS1710 controller provides an internal isolation switch which
allows the connection of two batteries. When entering battery backup operation, the battery with the
highest voltage is selected for use. If one battery should fail, the other would then supply energy to the
connected load. The switch to a redundant battery is transparent to circuit operation and to the user. In
applications where battery redundancy is not a major concern a single battery should be connected to the
BAT1 pin. The BAT2 battery pin must be grounded. When batteries are first connected to one or both of
the V_BAT pins V_CCO will not show the battery potential until V_CCI is applied and removed for the first time.
OPERATION - WRITE PROTECTION PROGRAMMING MODE
When the disable pin is connected to V_CCI or V_CCO, the DS1710 performs all of the functions described
earlier with the addition of a partition switch which selectively write protects blocks of memory. The state
of the DIS pin is strobed and latched as V_CCI crosses the power-fail trip point so that the DS1710
maintains its configuration during power loss. If the strobed value of DIS is high, the internal pulldown
resistor on the DIS pin will be disconnected in the power-fail state to eliminate the possibility of battery
discharge. The register controlling the partition switch is selected by recognition of a specific binary
pattern which is sent on address lines A_W - A_Z. These address lines are normally the four upper order
address lines being sent to RAM. The pattern is sent by 20 consecutive read cycles with the exact pattern
as shown in Table 1. Pattern matching must be accomplished using read cycles; any write cycles will
reset the pattern matching circuitry. If this pattern is matched perfectly, then the 21^st through 24^th read
cycle will load the partition switch. Since there are 16 possible write protected partitions, the size of each
partition is determined by the size of the memory. For example, a 128k X 8 memory would be divided
into 16 partitions of 128k/16 or 8k X 8. Each partition is represented by one of the 16 bits contained in
the 21^st through 24^th read cycle as defined by A_W through A_Z and shown in Table 2. A logical 1 in a bit
location sets that partition to write protect. A logical 0 in a bit location disables write protection. For
example, if during the pattern match sequence bit 22 on address pin A_X were a 1, this would cause the
partition register location for partition 5 to be set to a 1. This in turn would cause the DS1710 to inhibit
WEO from going low as WEI goes low whenever A_ZA_YA_XA_W=0101. Note that while setting the partition
register, data which is being accessed from the RAM should be ignored as the purpose of the 24 read
cycles is to set the partition switch and not for the purpose of accessing data from RAM. Also note that
on initial battery attach the partition register can power-up in any state.
3 of 14