CY8C56LP_13 Datasheet, PDF (96/120 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC®)

PSoC^® 5LP: CY8C56LP Family
Datasheet
Table 11-39. PGA AC Specifications^[61]
Parameter
Description
BW1
–3 dB bandwidth
SR1
Slew rate
e_n
Input noise density
Conditions
Min
Power mode = high,
6.7
gain = 1, input = 100 mV
peak-to-peak
Power mode = high,
3
gain = 1, 20% to 80%
Power mode = high,
–
V_DDA = 5 V, at 100 kHz
Typ
Max
Units
8
–
MHz
–
–
V/µs
43
–
nV/sqrtHz
Figure 11-63. Bandwidth vs. Temperature, at Different Gain
Settings, Power Mode = High
Figure 11-64. Noise vs. Frequency, Vdda = 5 V,
Power Mode = High
10
1000
1
100
0.1
-40
-20
0
20
40
Temperature, °C
Gain = 1
Gain = 24
60
80
Gain = 48
10
0.01
0.1
1
10
Frequency, kHz
100
1000
11.5.11 Temperature Sensor
Table 11-40. Temperature Sensor Specifications
Parameter
Description
Temp sensor accuracy
Conditions
Range: –40 °C to +85 °C
Min
Typ
Max
–
±5
–
11.5.12 LCD Direct Drive
Table 11-41. LCD Direct Drive DC Specifications^[61]
Parameter
I_CC
I_{CC_SEG}
V_BIAS
I_OUT
Description
Conditions
LCD Block (no glass)
Device sleep mode with wakeup at
400 Hz rate to refresh LCD, bus,
clock = 3MHz, Vddio = Vdda = 3 V, 8
commons, 16 segments, 1/5 duty
cycle, 40 Hz frame rate, no glass
connected
Current per segment driver
Strong drive mode
LCD bias range (V_BIAS refers to the main V_DDA ≥ 3 V and V_DDA ≥ V_BIAS
output voltage(V0) of LCD DAC)
LCD bias step size
LCD capacitance per segment/
common driver
V_DDA ≥ 3 V and V_DDA ≥ V_BIAS
Drivers may be combined
Maximum segment DC offset
Vdda ≥ 3V and Vdda ≥ Vbias
Output drive current per segment driver) V_DDIO = 5.5 V, strong drive mode
Min
Typ
–
81
–
260
2
–
– 9.1 × V_DDA
–
500
–
–
355
–
Max
–
–
5
–
5000
20
710
Units
°C
Units
μA
µA
V
mV
pF
mV
µA
Note
61. Based on device characterization (Not production tested).
Document Number: 001-84935 Rev. *C
Page 96 of 120