CY8C56LP_13 Datasheet, PDF (73/120 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC®)

PSoC^® 5LP: CY8C56LP Family
Datasheet
Table 11-12. SIO AC Specifications^[35]
Parameter
Description
Conditions
Min
TriseF
Rise time in Fast Strong Mode
Cload = 25 pF, V_DDIO = 3.3 V
–
(90/10%)
TfallF
Fall time in Fast Strong Mode
Cload = 25 pF, V_DDIO = 3.3 V
–
(90/10%)
TriseS
Rise time in Slow Strong Mode Cload = 25 pF, V_DDIO = 3.0 V
–
(90/10%)
TfallS
Fall time in Slow Strong Mode
Cload = 25 pF, V_DDIO = 3.0 V
–
(90/10%)
SIO output operating frequency
2.7 V < V_DDIO < 5.5 V, Unregulated 90/10% V_DDIO into 25 pF
–
output (GPIO) mode, fast strong
drive mode
1.71 V < V_DDIO < 2.7 V, Unregu- 90/10% V_DDIO into 25 pF
–
lated output (GPIO) mode, fast
strong drive mode
3.3 V < V_DDIO < 5.5 V, Unregulated 90/10% V_DDIO into 25 pF
–
output (GPIO) mode, slow strong
drive mode
Fsioout
1.71 V < V_DDIO < 3.3 V, Unregu- 90/10% V_DDIO into 25 pF
–
lated output (GPIO) mode, slow
strong drive mode
2.7 V < V_DDIO < 5.5 V, Regulated Output continuously switching into
–
output mode, fast strong drive mode 25 pF
1.71 V < V_DDIO < 2.7 V, Regulated Output continuously switching into
–
output mode, fast strong drive mode 25 pF
1.71 V < V_DDIO < 5.5 V, Regulated Output continuously switching into
–
output mode, slow strong drive 25 pF
mode
SIO input operating frequency
Fsioin
1.71 V < V_DDIO < 5.5 V
90/10% V_DDIO
–
Typ
Max Units
–
12
ns
–
12
ns
–
75
ns
–
60
ns
–
33
MHz
–
16
MHz
–
5
MHz
–
4
MHz
–
20
MHz
–
10
MHz
–
2.5
MHz
–
66
MHz
Figure 11-14. SIO Output Rise and Fall Times, Fast Strong
Mode, V_DDIO = 3.3 V, 25 pF Load
Figure 11-15. SIO Output Rise and Fall Times, Slow Strong
Mode, V_DDIO = 3.3 V, 25 pF Load
Note
35. Based on device characterization (Not production tested).
Document Number: 001-84935 Rev. *C
Page 73 of 120