CY8C56LP_13 Datasheet, PDF (18/120 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC®)

PSoC^® 5LP: CY8C56LP Family
Datasheet
5.6 External Memory Interface
CY8C56LP provides an External Memory Interface (EMIF) for
connecting to external memory devices. The connection allows
read and write accesses to external memories. The EMIF
operates in conjunction with UDBs, I/O ports, and other
hardware to generate external memory address and control
signals. At 33 MHz, each memory access cycle takes four bus
clock cycles. Figure 5-1 is the EMIF block diagram. The EMIF
supports synchronous and asynchronous memories. The
CY8C56LP only supports one type of external memory device at
a time.
External memory is located in the Cortex-M3 external RAM
space; it can use up to 24 address bits. See Table 5-4 on page
19Memory Map on page 19. The memory can be 8 or 16 bits
wide. Cortex-M3 instructions can be fetched/executed from
external memory, although at a slower rate than from flash.
There is no provision for code security in external memory. If
code must be kept secure, then it should be placed in internal
flash. See Flash Security on page 16 and Device Security on
page 60.
Figure 5-1. EMIF Block Diagram
Data,
Address,
and Control
Signals
IO IF
Address Signals
I/O ^{External_ MEM_ ADDR[23:0]}
PORTs
Data Signals
I/O ^{External_ MEM_ DATA[15:0]}
PORTs
PHUB
Data,
Address,
and Control
Signals
Data,
Address,
and Control
Signals
Control Signals
I/O
PORTs
UDB
DSI Dynamic Output
Control
DSI to Port
EM Control
Signals
Other
Control
Signals
EMIF
Control
Document Number: 001-84935 Rev. *C
Page 18 of 120