CY8C56LP_13 Datasheet, PDF (69/120 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC®)

PSoC^® 5LP: CY8C56LP Family
Datasheet
11.4 Inputs and Outputs
Specifications are valid for –40 °C ≤ T_A ≤ 85 °C and T_J ≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted. Unless otherwise specified, all charts and graphs show typical values.
When the power supplies ramp up, there are low-impedance connections between each GPIO pin and its V_DDIO supply. This causes
the pin voltages to track V_DDIO until both V_DDIO and V_DDA reach the IPOR voltage, which can be as high as 1.45 V. At that point the
low-impedance connections no longer exist, and the pins change to their normal NVL settings.
Also, if V_DDA is less than V_DDIO, a low-impedance path may exist between a GPIO and V_DDA, causing the GPIO to track V_DDA until
V_DDA becomes greater than or equal to V_DDIO.
11.4.1 GPIO
Table 11-9. GPIO DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
V_IH
V_IL
V_IH
V_IH
V_IL
V_IL
V_OH
V_OL
Rpullup
Input voltage high threshold CMOS Input, PRT[x]CTL = 0
0.7 × V_DDIO –
–
V
Input voltage low threshold CMOS Input, PRT[x]CTL = 0
–
– 0.3 × V_DDIO V
Input voltage high threshold LVTTL Input, PRT[x]CTL = 1,V_DDIO < 2.7 V 0.7 x V_DDIO –
–
V
Input voltage high threshold LVTTL Input, PRT[x]CTL = 1, V_DDIO ≥ 2.7 V
2.0
–
–
V
Input voltage low threshold LVTTL Input, PRT[x]CTL = 1,V_DDIO < 2.7 V
–
– 0.3 × V_DDIO V
Input voltage low threshold LVTTL Input, PRT[x]CTL = 1, V_DDIO ≥ 2.7 V
–
–
0.8
V
Output voltage high
I_OH = 4 mA at 3.3 V_DDIO
V_DDIO – 0.6 –
–
V
I_OH = 1 mA at 1.8 V_DDIO
V_DDIO – 0.5 –
–
V
Output voltage low
I_OL = 8 mA at 3.3 V_DDIO
–
–
0.6
V
I_OL = 3 mA at 3.3 V_DDIO
–
–
0.4
V
I_OL = 4 mA at 1.8 V_DDIO
–
–
0.6
V
Pull up resistor
3.5
5.6
8.5
kΩ
Rpulldown Pull down resistor
3.5
5.6
8.5
kΩ
I_IL
Input leakage current
(absolute value)^[30]
25 °C, V_DDIO = 3.0 V
C_IN
Input capacitance^[30]
GPIOs not shared with opamp outputs,
MHz ECO or kHzECO
–
–
2
nA
–
5
9
pF
GPIOs shared with MHz ECO or
kHzECO^[31]
–
5
9
pF
GPIOs shared with opamp outputs
–
10
20
pF
GPIOs shared with SAR inputs
–
10
20
pF
V_H
Input voltage hysteresis
(Schmitt–Trigger)^[30]
–
40
–
mV
Idiode
Rglobal
Current through protection
diode to V_DDIO and V_SSIO
Resistance pin to analog
global bus
25 °C, V_DDIO = 3.0 V
–
–
100
µA
–
320
–
Ω
Rmux
Resistance pin to analog mux 25 °C, V_DDIO = 3.0 V
bus
–
220
–
Ω
Notes
30. Based on device characterization (Not production tested).
31. For information on designing with PSoC 3 oscillators, refer to the application note, AN54439 - PSoC^® 3 and PSoC 5 External Oscillator.
Document Number: 001-84935 Rev. *C
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