W158_02 Datasheet, PDF (9/13 Pages) Cypress Semiconductor – Spread Spectrum System Frequency Synthesizer

W158
PCI Clock Outputs, PCI_F and PCI1:7 (Lump Capacitance Test Load = 30 pF)
Parameter
t_P
t_H
t_L
t_R
t_F
t_D
t_JC
Description
Period
High Time
Low Time
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Jitter, Cycle-to-Cycle
Test Condition/Comments
Measured on rising edge at 1.5V^[37]
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
Measured from 0.4V to 2.4V
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
Measured on rising edge at 1.5V. Maximum difference of
cycle time between two adjacent cycles.
Min. Typ. Max. Unit
30
ns
12
ns
12
ns
1
4 V/ns
1
4 V/ns
45
55 %
500 ps
t_SK
Output Skew
Measured on rising edge at 1.5V
500 ps
t_O
3V66 to PCI Clock
Covers all 3V66/PCI outputs. Measured on rising edge at 1.5
3 ns
Skew
1.5V. 3V66 leads PCI output.
t_q
CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising edge at 1.5
4 ns
1.5V. CPU leads PCI output.
f_ST
Frequency Stabilization Assumes full supply voltage reached within 1 ms from
from Power-up (cold power-up. Short cycles exist prior to frequency stabilization.
start)
3 ms
Z_o
AC Output Impedance Average value during switching transition. Used for deter-
15
Ω
mining series termination value.
REF Clock Outputs, REF0:1 (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
f
Frequency, Actual
Frequency generated by crystal oscillator
t_R
Output Rise Edge Rate
Measured from 0.4V to 2.4V
t_F
Output Fall Edge Rate
Measured from 2.4V to 0.4V
t_D
Duty Cycle
Measured on rising and falling edge at 1.5V
f_ST
Frequency Stabilization from Assumes full supply voltage reached within
Power-up (cold start)
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Z_o
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
Min.
0.5
0.5
45
Typ.
14.318
Max.
2
2
55
3
25
Unit
MHz
V/ns
V/ns
%
ms
Ω
48-MHZ Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
f
Frequency, Actual
Determined by PLL divider ratio (see m/n below)
f_D
Deviation from 48 MHz
(48.008 – 48)/48
m/n
PLL Ratio
(14.31818 MHz x 57/17 = 48.008 MHz)
t_R
Output Rise Edge Rate Measured from 0.4V to 2.4V
t_F
Output Fall Edge Rate
Measured from 2.4V to 0.4V
t_D
Duty Cycle
Measured on rising and falling edge at 1.5V
f_ST
Frequency Stabilization Assumes full supply voltage reached within 1 ms
from Power-up (cold start) from power-up. Short cycles exist prior to fre-
quency stabilization.
Z_o
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
Note:
37. PCI clock is CPU/4 for CPU = 133 MHz and CPU/3 for CPU = 100 MHz.
Min.
0.5
0.5
45
Typ.
48.008
+167
57/17
25
Max.
2
2
55
3
Unit
MHz
ppm
V/ns
V/ns
%
ms
Ω
Document #: 38-07164 Rev. *A
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