W158_02 Datasheet, PDF (4/13 Pages) Cypress Semiconductor – Spread Spectrum System Frequency Synthesizer

W158
Mode Selection Functions
The W158 supports the following operating modes controlled through the SEL133/100#, SEL0, and SEL1 inputs.
Table 2. Select Functions
SEL133/100#
SEL1
SEL0
Function
0
0
0
All Outputs Three-State
0
0
1
(Reserved)
0
1
0
Active 100-MHz, 48-MHz PLL Inactive
0
1
1
Active 100-MHz, 48-MHz PLL Active
1
0
0
Test Mode
1
0
1
(Reserved)
1
1
0
Active 133-MHz, 48-MHz PLL Inactive
1
1
1
Active 133-MHz, 48-MHz PLL Active
Table 3. Truth Table
SEL
133/100# SEL1 SEL0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
CPU
HI-Z
n/a
100 MHz
100 MHz
TCLK/2
n/a
133 MHz
133 MHz
CPUdiv2
HI-Z
n/a
50 MHz
50 MHz
TCLK/4
n/a
66 MHz
66 MHz
3V66
HI-Z
n/a
66 MHz
66 MHz
TCLK/4
n/a
66 MHz
66 MHz
PCI
HI-Z
n/a
33 MHz
33 MHz
TCLK/8
n/a
33 MHz
33 MHz
48MHz
HI-Z
n/a
HI-Z
48 MHz
TCLK/2
n/a
HI-Z
48 MHz
REF
IOAPIC
HI-Z
HI-Z
n/a
n/a
14.318 MHz 16.67 MHz
14.318 MHz 16.67 MHz
TCLK
TCLK16
n/a
n/a
14.318 MHz 16.67 MHz
14.318 MHz 16.67 MHz
Notes
2
3
4, 7, 8
5, 6
3
4, 7, 8
Table 4. Maximum Supply Current
Condition
Powerdown Mode
(PWRDWN#=0)
Max. 2.5V supply consumption
Max. discrete cap loads,
V_DDQ2=2.625V
All static inputs=V_DDQ3 or GND
100 µA
Max. 3.3V supply consumption
Max. discrete cap loads,
V_DDQ3=3.465V or GND
200 µA
Full Active 100 MHz
SEL133/100#=0
SEL1, 0=11
CPU_STOP#, PCI_STOP#=1
75 mA
160 mA
Full Active 133 MHz
SEL133/100#=0
SEL1, 0=11
CPU_STOP#, PCI_STOP#=1
90 mA
160 mA
Notes:
2. Provided for board level “bed of nails” testing.
3. 48-MHz PLL disabled to reduce component jitter.
4. Normal” mode of operation.
5. TCLK is a test clock over driven on the X1 input during test mode. TCLK mode is based on 133-MHz CPU select logic.
6. Required for DC output impedance verification.
7. Range of reference frequency is min.=14.316, nominal = 14.31818 MHz, max.=14.32 MHz.
8. Frequency accuracy of 48 MHz is +167 PPM to match USB default.
Document #: 38-07164 Rev. *A
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