CY14C064I_13 Datasheet, PDF (9/40 Pages) Cypress Semiconductor – 64-Kbit (8 K x 8) Serial (I2C) nvSRAM with Real Time Clock

CY14C064I
CY14B064I
CY14E064I
connected to ground. Power Up RECALL operation cannot be
disabled in any case.
■ SLEEP: SLEEP instruction puts the nvSRAM in a sleep mode.
When the SLEEP instruction is registered, the nvSRAM takes
t_SS time to process the SLEEP request. Once the SLEEP
command is successfully registered and processed, the
nvSRAM toggles HSB LOW, performs a STORE operation to
secure the data to nonvolatile memory and then enters into
SLEEP mode. Whenever nvSRAM enters into sleep mode, it
initiates non volatile STORE cycle which results in losing an
endurance cycle per sleep command execution. A STORE
cycle starts only if a write to the SRAM has been performed
since the last STORE or RECALL cycle.
The nvSRAM enters into sleep mode in this manner:
1. The master sends a START command.
2. The master sends Control Registers Slave device ID with I²C
write bit set (R/W = ’0’).
3. The slave (nvSRAM) sends an ACK back to the master.
4. The master sends Command Register address (0xAA).
5. The slave (nvSRAM) sends an ACK back to the master.
6. The master sends Command Register byte for entering into
sleep mode.
7. The slave (nvSRAM) sends an ACK back to the master.
8. The master generates a STOP condition.
Once in sleep mode, the device starts consuming I_ZZ current
t_SLEEP time after SLEEP instruction is registered. The device is
not accessible for normal operations until it is out of sleep mode.
The nvSRAM wakes up after t_WAKE duration after the device
slave address is transmitted by the master.
Transmitting any of the three slave addresses wakes the
nvSRAM from sleep mode. The nvSRAM device is not
accessible during t_SLEEP and t_WAKE interval and any attempt to
access the nvSRAM device by the master is ignored and
nvSRAM sends NACK to the master. An alternate method of
determining when the device is ready is for the master can send
read or write commands and look for an ACK.
Write Protection (WP)
The Write Protect (WP) pin is an active HIGH pin and protects
the entire memory and all registers from write operations. To
inhibit all the write operations, this pin must be held HIGH. When
this pin is HIGH, all memory and register writes are prohibited
and the address counter is not incremented. This pin is internally
pulled LOW and, therefore, can be left open if not used.
AutoStore Operation
The AutoStore operation is a unique feature of nvSRAM that
automatically stores the SRAM data to QuantumTrap cells
during power-down. This STORE makes use of an external
capacitor (V_CAP) and enables the device to safely STORE the
data in the nonvolatile memory when power goes down.
During normal operation, the device draws current from V_CC to
charge the capacitor connected to the V_CAP pin. When the
voltage on the V_CC pin drops below V_SWITCH during power-down,
the device inhibits all memory accesses to nvSRAM and
automatically performs a conditional STORE operation using the
charge from the V_CAP capacitor. The AutoStore operation is not
initiated if no write cycle has been performed since the last
STORE or RECALL.
Note If a capacitor is not connected to V_CAP pin, AutoStore must
be disabled by issuing the AutoStore Disable instruction
specified in Command Register on page 8. If AutoStore is
enabled without a capacitor on V_CAP pin, the device attempts an
AutoStore operation without sufficient charge to complete the
Store. This will corrupt the data stored in nvSRAM as well as the
serial number and it will unlock the SNL bit.
Figure 10 shows the proper connection of the storage capacitor
(V_CAP) for AutoStore operation. See the DC Electrical
Characteristics on page 29 for the size of the V_CAP.
Figure 10. AutoStore Mode
VCC
0.1 uF
VCC
VCAP
VSS
VCAP
Hardware STORE and HSB pin Operation
The HSB pin in CY14X064I is used to control and acknowledge
STORE operations. If no STORE or RECALL is in progress, this
pin can be used to request a Hardware STORE cycle. When the
HSB pin is driven LOW, the device conditionally initiates a
STORE operation after t_DELAY duration. An actual STORE cycle
starts only if a write to the SRAM has been performed since the
last STORE or RECALL cycle. Reads and Writes to the memory
are inhibited for t_STORE duration or as long as HSB pin is LOW.
The HSB pin also acts as an open drain driver (internal 100 k
weak pull-up resistor) that is internally driven LOW to indicate a
busy condition when the STORE (initiated by any means) is in
progress.
Note After each Hardware and Software STORE operation HSB
is driven HIGH for a short time (t_HHHD) with standard output high
current and then remains HIGH by internal 100 k pull-up
resistor.
Note For successful last data byte STORE, a hardware STORE
should be initiated at least one clock cycle after the last data bit
D0 is received.
Upon completion of the STORE operation, the nvSRAM memory
access is inhibited for t_LZHSB time after HSB pin returns HIGH.
Leave the HSB pin unconnected if not used.
Hardware RECALL (Power Up)
During power-up, when V_CC crosses V_SWITCH, an automatic
RECALL sequence is initiated that transfers the content of
nonvolatile memory to the SRAM. The data may have been
Document Number: 001-68169 Rev. *F
Page 9 of 40