CY14C064I_13 Datasheet, PDF (13/40 Pages) Cypress Semiconductor – 64-Kbit (8 K x 8) Serial (I2C) nvSRAM with Real Time Clock

CY14C064I
CY14B064I
CY14E064I
Random Address Read
A random address read is performed by first initiating a write
operation and generating a Repeated START immediately after
the last address byte is acknowledged. The address counter is
set to this address and the next read access to this slave initiates
read operation from here. The master may terminate a read
operation after reading 1 byte or continue reading addresses
sequentially till the last address in the memory after which the
address counter rolls back to the start address 0x0000.
By Master
SDA Line
By nvSRAM
Figure 19. Random Address Single-Byte Read (except Hs-mode)
S
T
A
R _{Memory Slave Address}
T
Most Significant Address
Byte
Least Significant Address
Byte
Memory Slave Address
S 1 0 1 0 A2 A1 A0 0
X XX
Sr 1 0 1 0 A2 A1 A0 1
A
A
A
A
Data Byte
S
A^T
0
P
P
By Master
SDA Line
By nvSRAM
Figure 20. Random Address Multi-Byte Read (except Hs-mode)
S
T
A
R _{Memory Slave Address}
T
Most Significant Address
Byte
Least Significant Address
Byte
Memory Slave Address
S 1 0 1 0 A2 A1 A0 0
X XX
Sr 1 0 1 0 A2 A1 A0 1
A
S
A
A
A
T
A₀
P
P
Data Byte N
A
Data Byte 1
By Master
SDA Line
By nvSRAM
Figure 21. Random Address Single-Byte Read (Hs-mode)
S
T
A
R _{Hs-mode command}
T
Memory Slave Address
Most Significant Address
Byte
Least Significant Address
Byte
S 0 0 0 0 1 X X X Sr 1 0 1 0 A2 A1 A0 0 X X X
Memory Slave Address
Sr 1 0 1 0 A2 A1 A0 1
A
A
A
A
A
S
T
A0
P
P
Data Byte
Document Number: 001-68169 Rev. *F
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