CY14C064I_13 Datasheet, PDF (10/40 Pages) Cypress Semiconductor – 64-Kbit (8 K x 8) Serial (I2C) nvSRAM with Real Time Clock

CY14C064I
CY14B064I
CY14E064I
previously stored on the nonvolatile memory through a STORE
sequence.
A Power Up RECALL cycle takes t_FA time to complete and the
memory access is disabled during this time. HSB pin can be
used to detect the ready status of the device.
Write Operation
The last bit of the slave device address indicates a read or a write
operation. In case of a write operation, the slave device address
is followed by the memory or register address and data. A write
operation continues as long as a STOP or Repeated START
condition is generated by the master or if a NACK is issued by
the nvSRAM.
A NACK is issued from the nvSRAM under the following
conditions:
1. A valid Device ID is not received.
2. A write (burst write) access to a protected memory block
address returns a NACK from nvSRAM after the data byte is
received. However, the address counter is set to this address
and the following current read operation starts from this
address.
3. A write/random read access to an invalid or out-of-bound
memory address returns a NACK from the nvSRAM after the
address is received. The address counter remains unchanged
in such a case.
After a NACK is sent out from the nvSRAM, the write operation
is terminated and any data on the SDA line is ignored till a STOP
or a Repeated START condition is generated by the master.
For example, consider a case where the burst write access is
performed on Control Register Slave address 0x01 for writing the
serial number and continued to the address 0x09, which is a
read-only register. The device returns a NACK and address
counter is not incremented. A following read operation is started
from the address 0x09. Further, any write operation which starts
from a write protected address (say, 0x09) is responded by the
nvSRAM with a NACK after the data byte is sent and set the
address counter to this address. A following read operation starts
from the address 0x09 in this case also.
Note In case user tries to read/write access an address that does
not exist (for example 0x0D in Control Register Slave or 0x3F in
RTC registers), nvSRAM responds with a NACK immediately
after the out-of-bound address is transmitted. The address
counter remains unchanged and holds the previous successful
read or write operation address.
A write operation is performed internally with no delay after the
eighth bit of data is transmitted. If a write operation is not
intended, the master must terminate the write operation before
the eighth clock cycle by generating a STOP or Repeated
START condition.
More details on write instructions are provided in the section
Memory Slave Access on page 10.
Read Operation
If the last bit of the slave device address is ‘1’, a read operation
is assumed and the nvSRAM takes control of the SDA line
immediately after the slave device address byte is sent out by
the master. The read operation starts from the current address
location (the location following the previous successful write or
read operation). When the last address is reached, the address
counter loops back to the first address.
In case of the Control Register Slave, whenever a burst read is
performed such that it flows to a non-existent address, the reads
operation loops back to 0x00. This is applicable, in particular, for
the Command Register.
Read operation can be ended using the following methods:
1. The master issues a NACK on the ninth clock cycle followed
by a STOP or a Repeated START condition on the tenth clock
cycle.
2. The master generates a STOP or Repeated START condition
on the ninth clock cycle.
More details on write instruction are provided in the section
Memory Slave Access on page 10.
Memory Slave Access
The following sections describe the data transfer sequence
required to perform read or write operations from nvSRAM.
Write nvSRAM
Each write operation consists of a slave address being
transmitted after the start condition. The last bit of slave address
must be set as ‘0’ to indicate a Write operation. The master may
write one byte of data or continue writing multiple consecutive
address locations while the internal address counter keeps
incrementing automatically. The address register is reset to
0x0000 after the last address in memory is accessed. The write
operation continues till a STOP or Repeated START condition is
generated by the master or a NACK is issued by the nvSRAM.
A write operation is executed only after nvSRAM receives all the
eight data bits. The nvSRAM sends an ACK signal after a
successful write operation. A write operation may be terminated
by the master by generating a STOP condition or a Repeated
START operation. If the master desires to abort the current write
operation without altering the memory contents, this should be
done using a START/STOP condition prior to the eighth data bit.
If the master tries to access a write protected memory address
on the nvSRAM, a NACK is returned after the data byte intended
to write the protected address is transmitted and address counter
will not be incremented. Similarly, in a burst mode write
operation, a NACK is returned when the data byte that attempts
to write a protected memory location and the address counter is
not incremented.
Document Number: 001-68169 Rev. *F
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