CY14C064I_13 Datasheet, PDF (16/40 Pages) Cypress Semiconductor – 64-Kbit (8 K x 8) Serial (I2C) nvSRAM with Real Time Clock

CY14C064I
CY14B064I
CY14E064I
Control Registers Slave
The following sections describe the data transfer sequence
required to perform read or write operations from Control
Registers Slave.
Write Control Registers
To write the Control Registers Slave, the master transmits the
Control Registers Slave address after generating the START
condition. The write sequence continues from the address
location specified by the master till the master generates a STOP
condition or the last writable address location.
If a non-writable address location is accessed for write operation
during a normal write or a burst, the slave generates a NACK
after the data byte is sent and the write sequence terminates.
Any following data bytes are ignored and the address counter is
not incremented.
If a write operation is performed on the Command Register
(0xAA), the following current read operation also begins from the
first address (0x00) as in this case, the current address is an
out-of-bound address. The address is not incremented and the
next current read operation begins from this address location. If
a write operation is attempted on an out-of-bound address
location, the nvSRAM sends a NACK immediately after the
address byte is sent.
Further, if the serial number is locked, only two addresses (0xAA
or Command Register, and 0x00 or Memory Control Register)
are writable in the Control Registers Slave. On a write operation
to any other address location, the device will acknowledge
command byte and address bytes but it returns a NACK from the
control Registers Slave for data bytes. In this case, the address
will not be incremented and a current read will happen from the
last acknowledged address.
The nvSRAM Control Registers Slave sends a NACK when an
out of bound memory address is accessed for write operation, by
the master. In such a case, a following current read operation
begins from the last acknowledged address.
By Master
SDA Line
By nvSRAM
Figure 29. Single-Byte Write into Control Registers
S
T
A
Control Registers
R
Slave Address
T
Control Register Address
Data Byte
S 0 0 1 1 A2 A1 A0 0
A
A
S
T
0
P
P
A
By Master
SDA Line
By nvSRAM
Figure 30. Multi-Byte Write into Control Registers
S
T
A
Control Registers
R
Slave Address
T
Control Register Address
Data Byte
S 0 0 1 1 A2 A1 A0 0
A
A
A
S
T
Data Byte N
0
P
P
A
Document Number: 001-68169 Rev. *F
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