CY82C693UB Datasheet, PDF (89/164 Pages) Cypress Semiconductor – hyperCache TM / Stand-Alone PCI Peripheral Controller with USB

PRELIMINARY
CY82C693UB
hyperCache Specific (Not Required by SFF-8038i) Registers
The following registers define options/functions that are not explicitly covered by the SFF-8038i spec. Nonetheless, these registers
should be programmed for complete operation.
Bus Master IDE Channel 0 Configuration Register (I/O Address 22H with Data = 30 (Index Port); I/O Address 23H is the
Data Port)
Bit
Function
Default
7:3
Reserved. Will Return ’00000’ on read.
00000
2
IDE DMA Transfer Mode:
0
0:
Multiple
1:
Single
1:0
IDE DMA Transfer Speed Mode:
00
00:
Mode 0
01:
Mode 1
10:
Mode 2
11:
Reserved
Bus Master IDE Channel 1 Configuration Register (I/O Address 22H with Data = 31 (Index Port); I/O Address 23H is the
Data Port)
Bit
Function
Default
7:3
Reserved. Will Return ’00000’ on read.
00000
2
IDE DMA Transfer Mode:
0
0:
Multiple
1:
Single
1:0
IDE DMA Transfer Speed Mode:
00
00:
Mode 0
01:
Mode 1
10:
Mode 2
11:
Reserved
Bus Master IDE TimeOut Register (I/O Address 22H with Data = 32 (Index Port); I/O Address 23H is the Data Port) - Write
Only
Bit
Function
Default
7:0
IDE DMA time out counter value.
28H
This register provides the terminal count on a counter with a 14.318 MHz clock input.
Therefore, to find the timeout period, multiply the value in this register by 69.8 ns.
Bus Master IDE Test Register (I/O Address 22H with Data = 33 (Index Port); I/O Address 23H is the Data Port)
Bit
Function
Default
7:0
Undefined on read; Must write 00000000 on writes to this register.
00000000
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