CY82C693UB Datasheet, PDF (30/164 Pages) Cypress Semiconductor – hyperCache TM / Stand-Alone PCI Peripheral Controller with USB

PRELIMINARY
CY82C693UB
ISA Interface Signals (continued)
Name
I/O
DRQ[3:0]
I
DACK0/TSTM
I/O
DACK1/TSTM0
I/O
DACK2/TSTM1
I/O
DACK3/DISPSEL I/O
DACK5/KBSEL
I/O
/GPIO9
DACK6/RTCSEL I/O
/GPIO10
Description
ISA DMA/Master Request Inputs: These signals are used by external ISA peripherals
to request mastership of the ISA bus for DMA or ISA MASTER cycles. These signals
can also be programmed to be time multiplexed (based on ATCLK) to free DRQ[7:5]
for GPIO. If they are multiplexed, the multiplexed version of DREQ3 and DREQ7 (with
DREQ3 passed through when ATCLK is LOW) should be connected to the DRQ3 pin,
the multiplexed version of DREQ1 and DREQ6 (with DREQ1 active when ATCLK is
LOW) should be tied to the DRQ1 pin, the multiplexed version of DREQ0 and DREQ5
(with DREQ0 active when ATCLK is LOW) should be tied to the DRQ0 pin, and DREQ2
should be tied directly to the DRQ2 pin.
ISA DMA/Master 0 Acknowledge/Test Mode Enable: This signal is used by the
CY82C693UB to grant ISA bus mastership to external ISA peripherals for DMA or ISA
MASTER cycles. At power-up, this pin should be pulled-down through a 1K Ohm re-
sistor to enable test mode. For normal operation, this pin should not be pulled-down.
This signal can also be programmed to generate a DMA acknowledge code that can
be sent to the Input A input of a ’138 type TTL 1 of 8 decoder. By programming this
input to generate a coded output, DACK[7:5] are free to become GPIO.
ISA DMA/Master 1 Acknowledge Input/Test Mode Select 0: This signal is used by the
CY82C693UB to grant ISA bus mastership to external ISA peripherals for DMA or ISA
MASTER cycles. At power-up, this pin should be pulled-down through a 1K Ohm re-
sistor or not pulled-down to select between the different test modes.
This signal can also be programmed to generate a DMA acknowledge code that can
be sent to the Input B input of a ’138 type TTL 1 of 8 decoder. By programming this
input to generate a coded output, DACK[7:5] are free to become GPIO.
ISA DMA/Master 2 Acknowledge/Test Mode Select 1: This signal is used by the
CY82C693UB to grant ISA bus mastership to external ISA peripherals for DMA or ISA
MASTER cycles. At power-up, this pin should be pulled-down through a 1K Ohm re-
sistor not pulled-down to select between the different test modes.
This signal can also be programmed to generate a DMA acknowledge code that can
be sent to the Input C input of a ’138 type TTL 1 of 8 decoder. By programming this
input to generate a coded output, DACK[7:5] are free to become GPIO.
ISA DMA/Master 3 Acknowledge Input/Display Type Select: This signal is used by the
CY82C693UB to grant ISA bus mastership to external ISA peripherals for DMA or ISA
MASTER cycles. At power-up, this pin should be pulled-down through a 1K Ohm re-
sistor or left floating to select between CGA and Monochrome monitors (acts as the
keyboard controller Mono/Color pin).
This signal can also be programmed to generate an enable to a ’138 type TTL 1 of 8
decoder. By programming this input to generate the enable, glitches are prevented
when the code signals switch.
ISA DMA/Master 5 Acknowledge Input/Internal Keyboard Controller Enable/General
Purpose I/O 9: This signal is used by the CY82C693UB to grant ISA bus mastership
to external ISA peripherals for DMA or ISA MASTER cycles. At power-up, this pin
should be pulled-down through a 1K Ohm resistor to disable the internal keyboard
controller if an external keyboard controller is desired.
This signal can be used as a GPIO if DACK[3:0] are programmed to connect to an
external ’138 type TTL 1 of 8 decoder.
ISA DMA/Master 6 Acknowledge Input/Internal Real Time Clock Enable/General Pur-
pose I/O 10: This signal is used by the CY82C693UB to grant ISA bus mastership to
external ISA peripherals for DMA or ISA MASTER cycles. At power-up, this pin should
be pulled-down through a 1K Ohm resistor to disable the internal RTC if an external
RTC is desired. NOTE: external RTC support is available through bond option (sepa-
rate part number). Please contact Cypress if the use of an external RTC is desired.
This signal can be used as a GPIO if DACK[3:0] are programmed to connect to an
external ’138 type TTL 1 of 8 decoder.
30